Consider the circuit below. What is the logic function implemented by the circui

Question

Consider the circuit below. What is the logic function implemented by the circuit? Size the devices so that the equivalent resistance of the worst case pull-up and pull-down paths are the same as that of an inverter with (W/L)_n = 3 and (W/L)_p = 6 (the inverter is balanced in pull-up and pull-down). Applying the sizing obtained in b), what are the input patterns that give the worst case t_pHL and t_PLH? Regardless of MOS operation region, assume 1 unit of (W/L) will provide C capacitance seen at source or drain, and the equivalent resistance of a (W/L)_n = 1 NMOS device is R. Obtain t_pHL and t_pLH using Elmore delay

Explanation / Answer

a) the logic function

Y=((A+B).C.D)'

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