I only need Problem 6, problem 5 is only there because it is relevent to problem
ID: 1716617 • Letter: I
Question
I only need Problem 6, problem 5 is only there because it is relevent to problem 6.
5. Write a VHDL module to implement an 8-bit serial-in, serial-out right-left shift register with inputs RSI, LSI, En, R, and CLK. RSO and LSO are the serial outputs, so they should be the rightmost and leftmost bits of the register. However, the values of the other flip-flops inside the register should not appear on the outputs. When En = 1, at the rising edge of the clock, the register shifts right if R = 1 or left if R = 0. RSI should be the shift-in input if R = 1, and LSI should be the shift-in input if R = 0. When En = 0, the register holds its state. There should also be an asynchronous active low clear input ClrN.
6. Work Problem 5, but change the register to 6 bits, remove the input En, and add an input L. At the rising edge of the clock, if R = 1 and L = 0, the register shifts right. If R = 0 and L = 1, the register shifts left. If R = L = 0 or R = L = 1, the register holds its state.
Explanation / Answer
Please find the code as below:
library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(CLK, RSI , LSI , R ,L, ClrN: in std_logic;
RSO , LSO : out std_logic);
end shift;
architecture archi of shift is
signal temp: std_logic_vector(5 downto 0);
begin
process (CLK,ClrN)
begin
if(CLrN = '0') then
temp <= "000000";
end if;
if (CLK'event and CLK='1') then
if(R = '0' and L = '1') then
temp(5 downto 1) <= temp(4 downto 0);
temp(0) <= LSI;
end if;
if(R = '1' and L = '0') then
temp(4 downto 0) <= temp(5 downto 1);
temp(5) <= RSI;
end if;
if((R = '0' and L = '1' ) or (R='1' and L = '0')) then
temp(5 downto 0) <= temp(5 downto 0);
end if;
end if;
end process;
RSO <= temp(0);
LSO <= temp(5);
end archi;
it is making shift left when R = 0 and L = 1 and shift right when R = 1 and L = 0 and holds the data when R = L = 0 or R = L = 1