Question
Can someone explain how to do this problem?
A NOR gate has been added as a feedback path for the shift register shown below. The outputs of the circuit are q[3] - q[0]. The initial state of the shift register is provided as the second row of Table 1. If rows 3 -13 of Table 1 correspond to consecutive rising edges of the mclk signal, complete the table by indicating what the output will be at each of these clock ticks. Assume that the clr signal is low. Table 1: Transition table showing the shift register output at each clock tick.
Explanation / Answer
q[3] q[2] q[1] q[0]
1 1 0 1
0 1 1 0
0 0 1 1
0 0 0 1
0 0 0 0
1 0 0 0
1 1 0 0
0 1 1 0
0 0 1 1
0 0 0 1
0 0 0 0