Please help: write the verilog code to assign zero delays (which is the default)
ID: 1846954 • Letter: P
Question
Please help: write the verilog code to
assign zero delays (which is the default) and simulate using the imputs in Fugure P5.7. 2) assign delays of 1ns to each gate and simulate with the same inputs. 3) assign a delay of 1ns to the inverter and 2ns to all other gates and simulate with the same inputs. 4) assign rise delay of 1ns and a fall delay of 2ns to each gate and simulate with the same inputs. In simulations 2)-4) note one difference in . Please note the differences in the simulations and choose one difference in Q for each simulation compared to first simulation and explain why that difference occurs.
Explanation / Answer
1)module d_latch (d, q, qbar, wen);
input d, wen;
output q, qbar;
wire dbar, r, s;
inv1: not(dbar, d);
nand1: nand(s, d, wen);
nand2: nand(r, dbar, wen);
nand3: nand(q, s, qbar);
nand4: nand(qbar, r, q);
endmodule
2)module d_latch (d, q, qbar, wen);
input d, wen;
output q, qbar;
wire dbar, r, s;
inv1: #1 not(dbar, d);
nand1:#1 nand(s, d, wen);
nand2:#1 nand(r, dbar, wen);
nand3:#1 nand(q, s, qbar);
nand4:#1 nand(qbar, r, q);
endmodule
3)module d_latch (d, q, qbar, wen);
input d, wen;
output q, qbar;
wire dbar, r, s;
inv1:#1 not(dbar, d);
nand1:#2 nand(s, d, wen);
nand2:#2 nand(r, dbar, wen);
nand3:#2 nand(q, s, qbar);
nand4:#2 nand(qbar, r, q);
endmodule
4)module d_latch (d, q, qbar, wen);
input d, wen;
output q, qbar;
wire dbar, r, s;
inv1:#(1,2) not(dbar, d);
nand1:#(1,2) nand(s, d, wen);
nand2:#(1,2) nand(r, dbar, wen);
nand3:#(1,2) nand(q, s, qbar);
nand4:#(1,2) nand(qbar, r, q);
endmodule
5) its sequential circuit which is depends time, where the time delay of each gate differ, the ouput make difffer, because that time differnce period wrong o/p is given as feedback which employing input,
Its known RACE around condition.