Carry Lookahead Adder in VHDL Implement a 5-bit carry lookahead adder in LogicWo

Question

Carry Lookahead Adder in VHDL


Implement a 5-bit carry lookahead adder in LogicWorks using VHDL. You must write your own code.
Do use code from the internet and do not look at other groups' code.
Use the following two-input gate delays for your implementations:
XOR 15ns
AND 10ns
OR 10ns
NOT 6ns
You do not have to enumerate each two-input gate, but your delays should be correct. For example,
f = a + b + c would take 20ns using two-input OR gates. You may implement this in VHDL with the
statement f<=a or b or c after 20ns.
You must use the data
ow model discussed in class. Implementations that use procedures will get a
zero.
You may not use the VHDL addition operator (+). Implementations that use + will get a zero.
Test your implementation to measure the time required to complete an add operation. Include a print-
out of the timing diagram for your implementation showing the most signicant bit (MSB) changing.
Compare the actual time with your results from Lab 6 in the Observations section of your report.
LogicWorks notes
{ Use the proper zoom to clearly show your results in the timing diagrams.
{ Print timing diagrams by selecting Simulation!Print Timing.

Explanation / Answer

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY c_l_addr IS PORT ( x_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); y_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); carry_in : IN STD_LOGIC; sum : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); carry_out : OUT STD_LOGIC ); END c_l_addr; ARCHITECTURE behavioral OF c_l_addr IS SIGNAL h_sum : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL carry_generate : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL carry_propagate : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL carry_in_internal : STD_LOGIC_VECTOR(7 DOWNTO 1); BEGIN h_sum

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