Inputs a[3;0], b[3:0], s[3:0] Outputs y[3:0] Function s function 0 y = a +b, uns
ID: 1924862 • Letter: I
Question
Inputs a[3;0], b[3:0], s[3:0]
Outputs y[3:0]
Function s function
0 y = a +b, unsigned add
1 y = a AND b, bit-wise AND
2 y = NOT a, bit-wise NOT of input a; ignore input b
3 y = 0, ignore inputs a and b
Write a Verilog testbench that:
uses Verilog loop statements to exhaustively test your module by applying all possible input combinations.
uses Verilog if-else and case statement to check that the module’s output is correct for the applied input pattern, and uses $display to print a pass/fail message to the console for each applied pattern.
Check your testbench checker by sabotaging your module: introduce an error that causes an incorrect output for at least one input pattern, and verify that your checker catches the erroneous output and prints a “fail” message.
Explanation / Answer
module c1( input [3:0] a, input [3:0] b, input [3:0] s, output [3:0] y ); reg [3:0]temp; always begin if(s == 4'b0000) temp = a + b; else if(s == 4'b0001) temp = a&b; else if(s == 4'b0010) temp = !a; else temp = 0; end assign y = temp; endmodule