Inspect the following Verilog module, and add wires or regs where needed. The mo
ID: 1995937 • Letter: I
Question
Inspect the following Verilog module, and add wires or regs where needed. The module takes a 8bitsub and checks for negatives, zeros or overflow
error messeges
`ccz' is not a legal lvalue in this context.
`ccv' is not a legal lvalue in this context.
`ccn' is not a legal lvalue in this context.
`ccc' is not a legal lvalue in this context.
vlog_a: Note: Parsing failed. 4 error(s), 0 warning(s)
module condition_unit (result,carry_in,ccn,ccz,ccv,ccc) ;
input [7:0] result;
input carry_in;
output ccn;
output ccz ;
output ccv;
output ccc;
always @ ( result or carry_in)
begin
if (result==8'd0) begin // zero flag set
ccz=1;
end
else if (carry_in==1) begin // overflow
ccv=1;
end
else if (result[7]==1'b1) begin // sign flag set
ccn=1;
end
ccc=0;
end
endmodule
Explanation / Answer
*** ccn,ccz,ccv,ccc outputs are assigend values in always block thats why these should be defined as registers.
module condition_unit (result,carry_in,ccn,ccz,ccv,ccc) ;
input [7:0] result;
input carry_in;
output ccn;
output ccz ;
output ccv;
output ccc;
wire carry_in;
reg ccn;
reg ccz ;
reg ccv;
reg ccc;
always @ ( result or carry_in)
begin
if (result==8'd0) begin // zero flag set
ccz=1;
end
else if (carry_in==1) begin // overflow
ccv=1;
end
else if (result[7]==1'b1) begin // sign flag set
ccn=1;
end
ccc=0;
end
endmodule