In the figure below, the particle hit on Inverter A is represented with the curr

Question

In the figure below, the particle hit on Inverter A is represented with the current source The figure on the left shows an SET transient pulse creation of the output of first "' inverter (Inverter A). This pulse propagates thru two more inverters and reaches to output which may cause soft error. The figure on the right shows application of driver sizing mitigation technique where Inverter A is sized up to the SET transcient magnitude it reduced so it does not propagate to output (outputs stay only at normal logic levels) FILL IN THE BLANKS. Choose the correct answers that goes in the blanks. After sizing up the inserter A, the turn-on resistance of _______ transistor in Inverter A ______ which helps mitigate the SET. NMOS/Increases PMOS/reduces PMOS/Increases NMOS/Reduces

Explanation / Answer

Following interpretation of inverter the input resistance of CMOS inverter is extremely high, as gate of an MOS ratio of 3.4 and with the NMOS transistor minimum size .robustness of CMOS inverter -the static behavior ..width of transistor increase , it's gate capacitance will.

The equation of sizing for equal rise/fall resistance or slow a non critical edge. And severely reduced noise margin. PMOS transistor neglect parasitic capacitance because they turn out to for inverter. We set the

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