For the circuit shown below, assume the delay through the registers is 2 (i.e. t

Question

For the circuit shown below, assume the delay through the registers is 2 (i.e. tpd= 2) ns and the minimum and maximum delays through each logic block are indicated inside the circles. Also the registers set-up time tsu = 1 ns and hold time thold = 2 ns. Write your answers in the space right below each question.

a) Determine the minimum clock period. Disregard clock skew. (2 points)

b) What is the maximum allowable positive clock skew between Reg. B and A (i.e. ?2 -?1>= 0)? (2 points)

c) What is the maximum allowable positive clock skew between Reg. C and B (i.e. ?3 -?2 >= 0)? (2 points)

d) What is the maximum allowable positive clock skew between Reg. C and A (i.e. ?3 -?1 >= 0)? (2 points)

e) What is the maximum allowable negative clock skew between Reg. B and A (i.e. ?2 - ?1 <= 0)? (2 points)

f) What is the maximum allowable negative clock skew between Reg. C and B (i.e. ?3 -?2 <= 0)? (2 points)

g) What is the maximum allowable negative clock skew between Reg. C and A (i.e. ?3 -?1 <= 0)? (2 points)

h) What is the minimum clock period if the clock is routed from left to right (i.e. ?3>= ?2>=?1)? (3 points)

i) What is the minimum clock period if the clock is routed from right to left (i.e. ?3<= ?2<=?1)? (3 points)

j) What is the minimum clock period if the clock is routed from the middle toward right and toward left (i.e. ?2<= ?3 & ?2<=?1)? (3 points)

Explanation / Answer

a).
Clock period > maximum combinational logic delay + register delay + setup time
and we encounter the maximum combinational logic delay between R1 (A) so
clock period > 26 + 2 + 1 =29ns
so minimum clock period is 29ns -----global.

b).
Clock period > maximum combinational logic delay + register delay + setup time
to find the skew between reg B(R2) and Reg A(R1)
For maximum allowable clock skew we can calculate the clock period required between these two
clock period > 21 + 2 + 1 =24ns
maximum allowable clock skew = global clock period - clock period required between these two register
maximum allowable clock skew =29 -24 = 5ns

c).
Clock period > maximum combinational logic delay + register delay + setup time
to find the skew between reg C(R3) and Reg B(R2)
For maximum allowable clock skew we can calculate the clock period required between these two
clock period > 22 + 2 + 1 =25ns
maximum allowable clock skew = global clock period - clock period required between these two register
maximum allowable clock skew = 29 -25 = 4ns

d).
Clock period > maximum combinational logic delay + register delay + setup time
to find the skew between reg C(R3) and Reg A(R1)
For maximum allowable clock skew we can calculate the clock period required between these two
clock period > 26 + 2 + 1 =29ns
maximum allowable clock skew = global clock period - clock period required between these two register
maximum allowable clock skew = 29 -29 = 0ns

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