Create a TestBench for this Garage Door Controller in VHDL: library IEEE; use IE
ID: 2073117 • Letter: C
Question
Create a TestBench for this Garage Door Controller in VHDL:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity garage_door_controller is
port (
remt, sen1, sen2, clk, rst : in std_logic;
ctr : out std_logic_vector (1 downto 0));
end garage_door_controller;
architecture Behavioral of garage_door_controller is
type state is (closed1, closed2, opening1, opening2, open1, open2, closing1, closing2);
signal pr_state, nx_state : state;
begin
--FSM state register:
process (clk, rst)
begin
if rst = '1' then
pr_state <= closed1;
elsif rising_edge(clk) then
pr_state <= nx_state;
end if;
end process;
--FSM combinational logic
process (pr_state, remt, sen1, sen2)
begin
case pr_state is
when closed1 =>
ctr <= "0-";
if remt = '0' then
nx_state <= closed2;
else
nx_state <= closed1;
end if;
when closed2 =>
ctr <= "0-";
if remt = '1' then
nx_state <= opening1;
else
nx_state <= closed2;
end if;
when opening1 =>
ctr <= "10";
if sen1 = '1' then
nx_state <= open1;
elsif remt = '0' then
nx_state <= opening2;
else
nx_state <= opening1;
end if;
when opening2 =>
ctr <= "10";
if remt = '1' or sen1 = '1' then
nx_state <= open1;
else
nx_state <= opening2;
end if;
when open1 =>
ctr <= "0-";
if remt = '0' then
nx_state <= open2;
else
nx_state <= open1;
end if;
when open2 =>
ctr <= "0-";
if remt = '1' then
nx_state <= closing1;
else
nx_state <= open2;
end if;
when closing1 =>
ctr <= "11";
if sen2 = '1' then
nx_state <= closed1;
elsif remt = '0' then
nx_state <= closing2;
else
nx_state <= closing1;
end if;
when closing2 =>
ctr <= "11";
if remt = '1' or sen2 = '1' then
nx_state <= closed1;
else
nx_state <= closing2;
end if;
end case;
end process;
end Behavioral;
Explanation / Answer
TEST BENCH FOR GARAGE DOOR CONTROL :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY test_tb IS
END test_tb;
ARCHITECTURE behavior OF test_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT test --'test' is the name of the module needed to be tested.
--just copy and paste the input and output ports of your module as such.
port (
remt, sen1, sen2, clk, rst : in std_logic;
ctr : out std_logic_vector (1 downto 0));
end component;
begin
--FSM state register:
process (clk, rst)
begin
if rst = '1' then
pr_state <= closed1;
elsif rising_edge(clk) then
pr_state <= nx_state;
end if;
end process;
--FSM combinational logic
process (pr_state, remt, sen1, sen2)
begin
case pr_state is
when closed1 =>
ctr <= "0-";
if remt = '0' then
nx_state <= closed2;
else
nx_state <= closed1;
end if;
when closed2 =>
ctr <= "0-";
if remt = '1' then
nx_state <= opening1;
else
nx_state <= closed2;
end if;
when opening1 =>
ctr <= "10";
if sen1 = '1' then
nx_state <= open1;
elsif remt = '0' then
nx_state <= opening2;
else
nx_state <= opening1;
end if;
when opening2 =>
ctr <= "10";
if remt = '1' or sen1 = '1' then
nx_state <= open1;
else
nx_state <= opening2;
end if;
when open1 =>
ctr <= "0-";
if remt = '0' then
nx_state <= open2;
else
nx_state <= open1;
end if;
when open2 =>
ctr <= "0-";
if remt = '1' then
nx_state <= closing1;
else
nx_state <= open2;
end if;
when closing1 =>
ctr <= "11";
if sen2 = '1' then
nx_state <= closed1;
elsif remt = '0' then
nx_state <= closing2;
else
nx_state <= closing1;
end if;
when closing2 =>
ctr <= "11";
if remt = '1' or sen2 = '1' then
nx_state <= closed1;
else
nx_state <= closing2;
--declare inputs and initialize them
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--declare outputs and initialize them
signal count : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: test PORT MAP (
clk => clk,
count => count,
reset => reset
);
-- Clock process definitions( clock with 50% duty cycle is generated here.
clk_process :process
begin
clk <= '0';
wait for clk_period/2; --for 0.5 ns signal is '0'.
clk <= '1';
wait for clk_period/2; --for next 0.5 ns signal is '1'.
end process;
-- Stimulus process
stim_proc: process
begin
wait for 7 ns;
reset <='1';
wait for 3 ns;
reset <='0';
wait for 17 ns;
reset <= '1';
wait for 1 ns;
reset <= '0';
wait;
end if;
end case;
end process;
end Behavioral;
this is the test bench for vhdl program of garage door control