Design a VHDL module for each of the following circuits. Your solutions should i
ID: 2079024 • Letter: D
Question
Design a VHDL module for each of the following circuits. Your solutions should include
VHDL source code with comments. Assume positive edge trigger for all flip-flops. Use a
text editor that will replace tabs with spaces for all your VHDL code.
3. Sixteen Bit Up/Down Counter Inputs: clock, reset, ud Outputs: 16-bit counter value Implement all 16-bits in a single VHDL process. The reset signal should synchronously reset the counter to zero. When ud 1', the counter should ncrement on each clock cycle. When ud '0', the counter should decrement on each clock cycle.Explanation / Answer
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY UPDOWN IS
PORT(CLOCK,RESET,UD:IN STD_LOGIC; --INPUT CLOCK, RESET AND UPDOWN COUNT
OUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); --OUTPUT REGISTER 16 BITS;
END UPDOWN;
ARCHITECTURE BEHAVIORAL OF UPDOWN IS
SIGNAL REG: STD_LOGIC_VECTOR(15 DOWNTO 0); --SIGNAL REG TO STORE INTERMEDIATE RESULTS;
BEGIN
PROCESS(CLOCK,RESET)
BEGIN
IF(RESET='1') THEN
REG<=(OTHERS=>'0');--IF RESET IS 1 THE COUNTER IS INITIALIZED TO 0;
ELSIF (CLOCK'EVENT AND CLOCK='1') THEN
--COUNTER VALUE CHANGES AT EVERY POSITIVE EDGE OF CLOCK;
IF (UD='1') THEN
REG<=REG+1; --COUNTER INCREMENTS IF UD=1;
ELSE
REG<=REG-1; -- COUNTER DECREMENTS IF UD=0;
END IF;
END IF;
END PROCESS;
OUT<=REG; -- REG VALUE STORED IS ACTUALLY SEEN AS OUT
END BEHAVIORAL;