Consider the timer modules of the PIC32. Assume “16-bit Synchronous Clock Counte
ID: 2079620 • Letter: C
Question
Consider the timer modules of the PIC32. Assume “16-bit Synchronous Clock Counter Mode using internal clock,” and assume a peripheral-bus clock frequency of fPBCLK = 10 MHz. Let D represent the user-selected prescale value (either 1, 2, 4, 8, 16, 32, 64, or 256) , and let P represent the value in the period register (PRx). Let fRollOver represent how frequently the timer register (TMRx) “rolls over” from P to 0. For all parts, show your work to a reasonable extent.
Problem 2. Consider the same timer and a peripheral-bus clock frequency of fr 10 MHz. If possible, find good choices for D and P in order to generate the over frequencies listed below. For each case, report the expected error in roll- over frequency, based on below formula. fRollover. Desired Error Desired Your goal is to select values for D and P that results in less than 1% error (Error 0.01 or less). For each case, calculate D, P, and Error, if at all possible. Show your work to a reasonable extent. a) Desired frequency 0.2 Hz b) Desired frequency 2 Hz c) Desired frequency- 20 Hz d) Desired frequency 200 HzExplanation / Answer
16-bit Synchronous Clock Counter Mode:-
The Synchronous Clock Counter operation provides the following capabilities:
• Elapsed time measurements
• Time delays
• Periodic timer interrupts
Type A and Type B timers have the ability to operate in Synchronous Clock Counter mode. In this mode, the input clock source for the timer is the internal peripheral bus clock, PBCLK. It is selected by clearing the clock source control bit, TCS (TxCON<1> = 0). Type A and Type B timers automatically provide synchronization to the peripheral bus clock; therefore, the Type A Timer Synchronous mode control bit TSYNC (T1CON<2>) is ignored in this mode.
Type A and Type B timers that use a 1:1 timer input clock prescale, operate at a timer clock rate that is same as the PBCLK, and which increments the TMR count register on every rising timer clock edge. The timer continues to increment until the TMR count register matches the PR period register value. The TMR count register resets to 0x0000 on the next timer clock cycle, and then continues to increment and repeats the period match until the timer is disabled. If the PR period register value = 0x0000, the TMR count register resets to 0x0000 on the next timer clock cycle, but does not continue to increment.
Type A and Type B timers using a timer input clock prescale = N (other than 1:1) operate at a timer clock rate (PBCLK N), and the TMR count register increments on every Nth timer clock rising edge. For example, if the timer input clock prescale is 1:8, the timer increments on every eighth timer clock cycle. The timer continues to increment until the TMR count register matches the PR period register value. The TMR count register then resets to 0x0000 after ‘N’ more timer clock cycles, and then continues to increment and repeats the period match until the timer is disabled. If the PR period register value = 0x0000, the TMR count register resets to 0x0000 on the next Nth timer clock cycle, but will not continue to increment.
Type A timers generate a timer event one-half timer clock cycle (on the falling edge) after the TMR count register matches the PR period register value. Type B timers generate a timer event within one PBCLK, plus two SYSCLK system clock cycles after the TMR count register matches the PR period register value. Both Type A and Type B timer interrupt flag bits, TxIF, are set within one PBCLK, plus two SYSCLK cycles of this event, and if the timer interrupt enable bit TxIE is set, an interrupt is generated.
16-BIT SYNCHRONOUS COUNTER INITIALIZATION STEPS:-
The following steps must be performed to configure the timer for 16-bit Synchronous Timer mode.
1. Clear the ON control bit (TxCON<15> = 0) to disable the timer.
2. Clear the TCS control bit (TxCON<1> = 0) to select the internal PBCLK source.
3. Select the desired timer input clock prescale.
4. Load/Clear the timer register TMRx.
5. Load the period register PRx with the desired 16-bit match value.
6. If interrupts are used:
a) Clear the TxIF interrupt flag bit in the IFSx register.
b) Configure the interrupt priority and subpriority levels in the IPCx register.
c) Set the TxIE interrupt enable bit in the IECx register.
7. Set the ON control bit (TxCON<15> = 1) to enable the timer.
Eg:- T2CON = 0x0; // Stop timer and clear control register,
// set prescaler at 1:1, internal clock source
TMR2 = 0x0; // Clear timer register
PR2 = 0xFFFF; // Load period register
T2CONSET = 0x8000; // Start timer