Implement the following bit sequential Adder-Subtract or design. X and Y are two
ID: 2079803 • Letter: I
Question
Implement the following bit sequential Adder-Subtract or design. X and Y are two operand inputs and Z is for the control signal i.e. Z is the selection bit. When Z has value 0, the circuit is an adder meanwhile, the D flip-flop should be initialized to 0 for each addition. When Z has value 1, it performs subtraction meanwhile, the the D flip-flop should be initialized to 1 for each subtraction. Test your Adder-Subtract or circuit on the following operations and use the 4-bit Shift Register to store and display their results. (Start from the least significant bit and remember to initialize the D flip-flop accordingly) 0001 + 0011 = ? 0101 + 0010 = ? 0101 - 0011 = ? 0011 - 0101 = ? Four test cases above (with MSB and LSB labelled) Description of the testing procedure used for Question 3Explanation / Answer
The carry input signal role is played by D as it is acting like a delay block.
Explanation for 1. D=0 and Z=0. Z(xor)0011=0011.
Now, we can simply add them to find the result.
Explanation for 2. Similar to 1.
Explanation for 3.D=1 and Z=1. Thus, 0011(xor)1=1100(1's complement). Thus, 0101+1100+1(D)=0010.
Explanation for 4.Same as 3 with a modification that after coming to the result, we will find its 2's complement which will represent a negative value. That is, 0011-0101=0011+1010+1 where 1010+1 is the 2's complement of 0101. This is equal to 1110. Finding its 2's complement, we get 0010 or -2 as a result.