Assume the CLR input on a 47LVC2g74 register is asserted. What is the worst on c
ID: 2079832 • Letter: A
Question
Assume the CLR input on a 47LVC2g74 register is asserted. What is the worst on case propagation delay it the device is operating with VCC = 5V? 1.0 ns 4.1 ns 5.9 ns none of the above A counter has a count sequence of 0, 3, 11. 5, 2, 0, 3, 11, ... In the Karnaugh maps used to determine the logic equations for each D-type flip-flop input, how many don't care states are there? 8 9 10 11 none of the above A shift register performs serial to parallel conversion of a data stream is a type of binary counter is a type of up-down counter is an asynchronous device A counter has the following logic equations for the two D-typc flip-flops (Do is the least significant bit). What is the count sequence? D_0 = Q_1 xoplus Q_0, D-1 = Q_1^bar 0, 2, 1, 3, 0, .... 0, 1, 2, 3, 0, ... 0, 3, 1, 2, 0, ... 0, 1, 3, 2, 0, ....Explanation / Answer
10)Assume CLR input on a 74LVC2g74 register is asserted......
ans:
(b) 4.1ns
By observing switching Characteristics of 74LVC2g74 we get max 4.1ns of propagation delay for Vcc=5v.
11)
12) A shift register
ans:
(a) performs serial to parallel conversion of data stream
Shift Registers are used for data storage or for the movement of data, So they can convert the data from either a serial to parallel or parallel to serial format.