Please answer the following questions, show your work/detail about power gating.
ID: 2080687 • Letter: P
Question
Please answer the following questions, show your work/detail about power gating.
A Floating Point Unit in a CPU can be power gated since it can spend many CPU cycles in idle mode. This problem determines how long it needs to be off for the lowest energy consumption. In case 1, the FPU is not power gated; in case 2 it is power gated for a Toff duration (see following figures). You need to determine the break-even point for Toff (where the total energy is equal for both case1 and case2). Assumptions: Ileak2 = Ileak1/1000 VDD_OFF = VDD/10 Total FPU capacitance = C The PFET power gate IR droop is negligible Assume that you have 2 CMOS technology options at your disposal to use on a 1GHz CPU; the 1^st one gives you a total FPU leakage of 1mA @ 0.75 Volts and T = 30C in standby (with NO power gating). The 2^nd one gives you leakage reductions of 10X at the same voltage and temperature with no transistor performance loss. In addition, this FPU cannot be shut down for more than 1000 CPU cycles (1000ns) due to the workloads of interest. Is power gating still required using the lower leakage CMOS technology assuming a total FPU capacitance of 0.5nF (connected to its power supply) to be charged/discharged.Explanation / Answer
(a) At the break even point both the energies of case1 and case2 are equal E(energy)=V*I*t for case 1 at the break even point we have E=VDD*Ileak1*(toff-tc)-------------1 for case2 we have E=VDDoff*Ileak2*toff--------------2 equating 1 and 2 we get tc=0.99toff (b)when the voltage does not change but current reduces 10 times we get tc=0.9toff=900ns at 900 ns the breakeven point for toff occurs and the leakage current becomes 0.1mA This does not solve the problem of power loss because dynamic power is given by V^2*C*f which remains the same so power gating is not required.