I\'m trying to make an 8bit LFSR VHDL for my lab and I am not entirely sure how
ID: 2081583 • Letter: I
Question
I'm trying to make an 8bit LFSR VHDL for my lab and I am not entirely sure how to go about it.
I set SW15 and SW14 to reset and clock enable. Do we need more inputs(switches) for the LFSR?
entity LFSR is port
(
btnr : in std_logic ;
SW15 : in std_logic;
SW14 : in std_logic;
LD7 : out std_logic ;
LD6 : out std_logic ;
LD5 : out std_logic ;
LD4 : out std_logic ;
LD3 : out std_logic;
LD2 : out std_logic;
LD1 : out std_logic;
LD0 : out std_logic
);
end LFSR;
----------------------------------------------------------------------
-- Architecture
architecture LFSR_a of LFSR is
----------------------------------------------------------------------
component dff270_re is port
(
clk : in std_logic ;
clken : in std_logic ;
rst : in std_logic ;
d : in std_logic ;
q : out std_logic
);
end component;
-------------------------------------------------------
-- Internal Signal Declarations
-------------------------------------------------------
-- NONE
signal Q1 : std_logic;
signal Q2 : std_logic;
signal Q3 : std_logic;
signal Q4 : std_logic;
signal Q5 : std_logic;
signal Q6 : std_logic;
signal Q7 : std_logic;
signal Q8 : std_logic;
signal output3 : std_logic;
signal output2 : std_logic;
signal output1 : std_logic;
signal output : std_logic;
begin
dff270_re1_dut : dff270_re port map
(
clk => btnr ,
clken => SW14,
rst => SW15 ,
d => output3,
q => Q1
);
dff270_re2_dut : dff270_re port map
(
clk => btnr ,
clken => SW14 ,
rst => SW15,
d => Q1,
q => Q2
);
dff270_re3_dut : dff270_re port map
(
clk => btnr ,
clken => SW14 ,
rst => SW15,
d => Q2,
q => Q3
);
dff270_re4_dut : dff270_re port map
(
clk => btnr ,
clken => SW14 ,
rst => SW15,
d => Q3,
q => Q4
);
dff270_re5_dut : dff270_re port map
(
clk => btnr ,
clken => SW14 ,
rst => SW15,
d => Q4,
q => Q5
);
dff270_re6_dut : dff270_re port map
(
clk => btnr ,
clken => SW14 ,
rst => SW15,
d => Q5,
q => Q6
);
dff270_re7_dut : dff270_re port map
(
clk => btnr ,
clken => SW14 ,
rst => SW15,
d => Q6,
q => Q7
);
dff270_re8_dut : dff270_re port map
(
clk => btnr ,
clken => SW14 ,
rst => SW15,
d => Q7,
q => Q8
);
-------------------------------------------------------
-- Component Instantiations
-------------------------------------------------------
-- NONE
-------------------------------------------------------------
-- Begin Design Description of Gates and how to connect them
-------------------------------------------------------------
output <= Q6 XNOR Q8 ;
output1 <= output XNOR Q5;
output2 <= output1 XNOR Q4;
output3 <= output2;
LD0 <= Q1;
LD1 <= Q2;
LD2 <= Q3;
LD3 <= Q4;
LD4 <= Q5;
LD5 <= Q6;
LD6 <= Q7;
LD7 <= Q8;
end LFSR_a;
Explanation / Answer
8 bit LFSR with maximum polynomial generator will be 2^8-1=255
for the clock and reset
alway define the constant
constant Width :interger:=8
clk : std_logic :='0';
reset : std_logic:='1';
enable: std_logic:='0';