Design 2 Stage CMOS Operational Amplifier with the following specifications: VDD

ID: 2082760 • Letter: D

Question

Design 2 Stage CMOS Operational Amplifier with the following specifications: VDD = -VSS = 2.5V

Av > 10,000 V/V

Unity-gain bandwidth (GB) = 4 MHz Slew Rate (SR) > 10 V/s for CL = 10 pF

Input Common-Mode Range -1.0V Vicm 2.0V

Output Voltage Range +/- 1.7V

Power Dissipation PDISS < 3 mW

Device parameters: channel length for all devices L = 0.5m, Vtn = - Vtp = 0.5V, k’n = 200 A/V2, k’p = 80 A/V2, V’An = -V’Ap = 20V/m.

vov =0.1v (same vov for all transistors)

IREff = 30 microAmp

VoD G-y Q. La QI a - E4 g, Vis

Minimum value of compensation capacitor (Cc)=0.22*load capacitor(Cl)=0.22*10pF=2.2pF;

Choose Cc as 3pF,using slew rate (SR),calculate minimum value of tail current I5=(Cc*SR)=(3*10^-12)*(10*10^6)=30?A;

Design S3 for maximum input voltage specification=(W/L)_3=I5/[Kp*(Vdd-Vinmax-Vt03maxVt1min)^2]=30*10^-6/[80*10^-6(2.5-2-.65+.35)^2]=10;

(W/L)3=(W/L)4=10;

Next step design to calculate gm1:

gm1=unity gain bandwidth(GB)*compensation capasitor(Cc)=(4*10^6)*(2pi)*(3*10^-12)=75.40?s;

Now, (W/L)1=(W/L)2=gm1^2/(Kn*I5)=(75.40)^2/(200*30)~1;

VDS5=[Vinmin-Vss-VT1max-?(I5/?1)]..

By putting all of the values we get VDs5=0.25;

Using VDS5 calculate saturation relationship:

(W/L)5=2*I5/(Kn*VDS5^2)~5;

As we know gm6>=10*gm1=754?s;

(W/L)6=(754*10-6)^2/(30*150*10^-6)=127;

I6=gm6^2/(2*K6*(W/L)6)=90?A;