ID Score 1. (30 pts) Design a 3-bit counter Q12:00 with two low-active synchrono
ID: 2083387 • Letter: I
Question
ID Score 1. (30 pts) Design a 3-bit counter Q12:00 with two low-active synchronous reset signals (resetno and resetnl) and a high- active enable control (en). The counting sequence is or 1 3-5 7-1 When resetn0 is low and resetni is high, reset to state 0; when the resetno is high and resetni is low, reset to state l.Output z is same as the state. You may refer to the pseudo codes below to understand the exact function of the counter. if reset0 resetl 01 else if reset0 resetl 10 else a rising edge of clock if (en 1) Complete the following Verilog code: z12:0] module my counter01(clock, resetno, resetni, en, z); clock resetn0 resetnl endmoduleExplanation / Answer
module mycounter01(resetn0, resetn0, clock, en, z);
input resetn0, resetn1, en;
input clock;
output [2:0]z;
reg [2:0] z;
always @ (resetn0 or resetn1)
begin
if (resetn0 resetn1= 2'b01)
begin
z <= 3'b000;
end
else if (resetn0 resetn1= 2'b01)
begin
z <= 3'b001;
end
end
always @ (posedge clock or en)
if (en = 1)
begin
z<=z+2;
end
end
endmodule