Digital Clock ----------------------------------------------------- Introduction
ID: 2084353 • Letter: D
Question
Digital Clock ----------------------------------------------------- Introduction: In this homework, we will write verilog code for digital clock. Work to do: 1) Write your clock module as template shown below: -------------------------------------------------------------- module clock( input reset_n, //reset pin input clk_1sec, //1 sec clock input clk_1ms, //1 mili sec clock input mil_time, //mil time pin output reg [6:0] segment_data, // output 7 segment data output reg [2:0] digit_select // digit select ); ---------------------------------------------------------------- 2) Simulate clock behaviour using dofile. What to turn in: Tar file of your code. It should have a shell script which simulates the clock
Explanation / Answer
module clock(
input reset_n, //reset pin
input clk_1sec, //1 sec clock
input clk_1ms, //1 mili sec clock
input mil_time, //mil time pin
output reg [6:0] segment_data, // output 7 segment data
output reg [2:0] digit_select // digit select
);
reg [2:0] dig_sel = 3'b000;
integer counter_sec = 0;
integer counter_ms = 0;
integer count_1place = 0;
integer count_10place = 0;
integer output_seven = 0;
always@(clk_1sec) begin
if (reset_n)
counter_sec = 'd0;
else begin
counter_sec = counter_sec + 1;
if (counter_sec == 'd60)
counter_sec = 'd0;
end
end
always@(clk_1ms) begin
if (reset_n)
counter_ms = 'd0;
else begin
counter_ms = counter_ms + 1;
if (counter_ms == 'd100)
counter_ms = 'd0;
end
end
always@(mil_time) begin
if(mil_time) begin
count_1place = counter_ms/10;
dig_sel = 3'b001;
output_seven = count_1place;
#1000;
count_10place = count_1place/10;
dig_sel = 3'b010;
output_seven = count_10place;
#1000;
dig_sel = 3'b100;
output_seven = 0;
#1000;
count_1place = 0;
count_10place = 0;
end
else begin
count_1place = counter_sec/10;
dig_sel = 3'b001;
output_seven = count_1place;
#1000;
count_10place = count_1place/10;
dig_sel = 3'b010;
output_seven = count_10place;
#1000;
dig_sel = 3'b100;
output_seven = 0;
#1000;
count_1place = 0;
count_10place = 0;
end
end
always@(output_seven) begin
segment_data_conv(output_seven,segment_data);
end
always@(dig_sel) begin
digit_select = dig_sel ;
end
task segment_data_conv(input integer x,output reg[7:0] y);
begin
case (x) //abcdefg
0: y = 7'b1111110;
1: y = 7'b0110000;
2: y = 7'b1101101;
3: y = 7'b1111001;
4: y = 7'b0110011;
5: y = 7'b1011011;
6: y = 7'b1011111;
7: y = 7'b1110000;
8: y = 7'b1111111;
9: y = 7'b1111011;
default: y = 7'bx;
endcase
end
endtask
endmodule