I have no idea about this question. Please solve this question. The system shown
ID: 2084390 • Letter: I
Question
I have no idea about this question.
Please solve this question.
The system shown in Figure 12-50 is a waveform (function) generator. It uses four 256-point look-up tables in a 1-Kbyte ROM to store one cycle each of a sine wave (address 000-0FF), a positive slope ramp (address 100-lFF), a negative slope ramp (200- 2FF), and a triangle wave (300- 3FF). The phase relationship among the three output channels is controlled by the values initially loaded into the three counters. The critical timing parameters are tpd(ck-Q and O-Q max), counters E 10 ns, latches E 6 ns, and tAcc ROM E 20 ns. Study the diagram until you understand how it operates and then answer the following: (a) In below Figure, the three latches on the left perform a function that represents one of the basic building blocks of digital systems as presented in Chapter 9. Which function is it? (b) The four latches that are fed by the ROM serve to implement another basic building block of digital systems. Which function is it? (c) Why are the octal latches that feed the DACs necessary? (d) What number must be on the MOD 4 function select counter to produce each of the following waveforms: triangle, sine; negative ramp, positive ramp?Explanation / Answer
a) The binary counters presented here consists of three 8-bit latches (counters). The high or low load command causes the 24 bits (3x8 bits) input data on the data bus to be loaded simultaneously into the binary counters. Thus the address on the ROM is of fixed value and the output of the DAC will be held at the corresponding fixed voltage. In this way the function we require can be changed or swept pointwise by the external computer through which we provide the 8-bit data which is nothing but the address that is to be initialised in the ROM. Thus those three latches act as address decoder.
d
b) It is the control circuit which enables various components in the circuit. The output A acts as clock circuit for the counters. Also A acts as output enable for first counter, B acts as output enable for second counter and C acts as output enable for third counter. The RC timing circuit output is bubbled which means when this circuit is not activated it will clear first three latches so that it will now act on new sei of data for signal generation and preset for fourth latch. Also the output C is used to enable first three latches connected to the output of ROM so that when they are enabled their output gets latched to the second set of latches connected to the output of first set of latches. The DAC-out is used to enable second set of latches so that when enabled this set of latches provide the necessary output to the DAC.
c) The octal latches are necessary to provide the proper sequencing and also to minimize the time effect. There would be a delay in the DAC which providing an analog signal for a digital set of data. The ROM is faster than the DAC so it will provide the next set of input to DAC even before the DAC has not given the corresponding analog signal for the previous set of input and the DAC will get saturated. So to minimize this situation, the latches are provided so that proper sequencing can be maintained.
d) 00= triangular (neither variable is changing the output will be steep on both sides)
01= positive ramp
10= negative ramp
11=sine