I need to take this verilog code and make a new module to be used as a signed co
ID: 2085106 • Letter: I
Question
I need to take this verilog code and make a new module to be used as a signed comparator two's complement.
// 1-bit Comparator
module comparator_1(A, B, L, E, G);
// A & B are 2-bits to be compared.
input A, B;
//3 outputs: L = lesser than, E = equal to, G = greater than.
output L, E, G;
//Connect wires to inverter.
wire s1, s2;
//Create inverter of the circuit.
not X1 (s1, A);
not X2 (s2, B);
nand X3 (L, s1, B);
nand X4 (G, s2, A);
nand X5 (E, L, G);
endmodule
//4-bit Comparator
module comparator_4(Lo, Eo, Go, A, B, Li, Ei, Gi);
// A & B take 4-bits each.
input [3:0] A;
input [3:0] B;
// 3 inputs from the 1-bit comparators: Li = A < B, Gi = A > B, Ei = A = B.
input Li, Gi, Ei;
//3 outputs: Lo = A < B, Go = A > B, Eo = A = B.
output Lo, Go, Eo;
//Connect wires for every comparators.
wire [3:0]L; wire [3:0]E; wire [3:0]G;
wire s0, s1, s2, s3, s4, s5, s6, s7, s8;
// Configure every 1-bit converter.
comparator_1 comp0(A[0], B[0], L[0], E[0], G[0]);
comparator_1 comp1(A[1], B[1], L[1], E[1], G[1]);
comparator_1 comp2(A[2], B[2], L[2], E[2], G[2]);
comparator_1 comp3(A[3], B[3], L[3], E[3], G[3]);
//Gate level information form logic diagram.
or X1(s3, E[3], L[2]);
or X2(s2, E[3], E[2], L[1]);
or X3(s1, E[3], E[2], E[1], L[0]);
or X4(s0, E[3], E[2], E[1], E[0], ~Li);
nor X5(s4, E[3], E[2], E[1], E[0], ~Ei);
nand X6(s5, L[3], s0, s1, s2, s3);
nor X7(Go, s5, s4);
//Assign Equal output = wire s4 and Lesser than output = wire s5.
assign Eo = s4;
assign Lo = s5;
endmodule
module SCOMP4()
Explanation / Answer
For first one the answer is
not X1(s1,a) = 1,
not X2 (s2, B) = 1,
nand X3 (L, s1, B) = 1,
nand X4 (G, s2, A) = 0,
nand X5 (E, L, G) = 1