Implement the circuit X = A + BC, Y = BC0 , Z = A + Y in Verilog. 1) Implement t
ID: 2248199 • Letter: I
Question
Implement the circuit X = A + BC, Y = BC0 , Z = A + Y in Verilog.
1) Implement the circuit using structural modeling.
2) Implement the circuit using data-flow modeling.
3) Implement the circuit using behavioral modeling.
4) Design a testbench to test the above three circuits. Your testbench needs to include at least four different inputs. In your code, explain the inputs that you are testing, and the outputs that you anticipate to see for each of your three circuits. Attach screenshots for the waveforms of these three circuits. (Use the same testbench for all three circuits.)
Explanation / Answer
--OR MODULE--
module or_gate (x,y,z);
input x,y;
output z;
assign z=x||y;
end module
--AND MODULE--
module and_gate (x,y,z);
input x,y;
output z;
assign z=x&y;
end module
--NOT MODULE--
module not_gate (x,y);
input x;
output y;
assign y=!x;
end module
--MAIN MODULE FOR QUESTION NO.1 --
module fx(X,Y,Z,A,B,C);
output X,Y,Z;
input A,B,C;
and_gate u1(n1,B,C);
or_gate u2(X,n1,A);
and_gate u3(n2,B,C);
and_gate u4(Y,0,n2);
or_gate u5(Z,A,Y);
endmodule