Problem 5. Write Verilog code to implement the state table in table 5.1. Use two
ID: 2248354 • Letter: P
Question
Problem 5. Write Verilog code to implement the state table in table 5.1. Use two always blocks State changes should occur on the falling edge of the clock. Implement the Z1 and Z2 outputs using continuous assignment statements. Assume that the combinational part of the sequential circuit has a propagation delay of 10 ns and the propagation delay between the rising-edge of the clock and state register output is 5 ns Next State Output Present State ZoZ x0x1= 00 01 11 S2 S1 SO S1 SO S2 SO S1 S2 041 SO S1 S2 10 01 Table 5.1 State table for problem 5.Explanation / Answer
module sm1 (clk,rst,Z0,Z1,X0,X1);
input clk,rst,X0,X1;
output Z0,Z1;
reg [1:0] p_state,n_state;
reg out0,out1;
always @(negedge clk)
begin
if (rst)
p_state<=2'b00;
else
p_state<=n_state;
end
always @ (posedge clk)
begin
case (p_state)
2'b00: begin
{out0,out1} = #5 2'b00;
case ({X1,X0})
2'b00:n_state<=2'b10;
2'b01:n_state<=2'b01;
2'b10:n_state<=2'b00;
default:n_state<=2'b00;
endcase
end
2'b01: begin
{out0,out1} = #5 2'b10;
case ({X1,X0})
2'b00:n_state<=2'b01;
2'b01:n_state<=2'b00;
2'b10:n_state<=2'b10;
default:n_state<=2'b00;
endcase
end
2'b10: begin
{out0,out1} = #5 2'b01;
case ({X1,X0})
2'b00:n_state<=2'b00;
2'b01:n_state<=2'b01;
2'b10:n_state<=2'b10;
default:n_state<=2'b00;
endcase
end
default: begin
n_state<=2'b00;
end
endcase
end
assign #10 Z1 = out1;
assign #10 Z0 = out0;
endmodule