Chapter 9. 9.3 Multiple-of-5 circuit, design. Using an approach similar to the m
ID: 2248461 • Letter: C
Question
Chapter 9. 9.3 Multiple-of-5 circuit, design. Using an approach similar to the multiple-of-3 circuit of section 9.1 design a multilple-of-5 circuit that outputs true if and only if its eight-bit input is a multiple of 5. (12 marks) Additional: This example is in the lecture notes 9.4 Multilple-of-5 circuit, implementation. Code your design from exercise 9.3 in Verilog and exhaustively verify it with a testbench. (12 marks) Additional: By exhaustive, demonstrate such a piece of code such that it will go up to 5-bit answer, that is, show all multiples of 5 from 1 to 31. Include a comparison with the % operator that is available in Verilog. The display should show: . the input value of the Multiple of 5 module in Binary Coded Decimal (BCD) . the output value of the Multiple of 5 module in BCD » the value of the modulus as a decimal number. . a statement that is either string ISMULTIPLE or ISNOTMULTIPLE Such as: Input Output % Result 00001 00010 00011 00100 00101 00010 001 1 ISNOTMULTIPLE 010 2 ISNOTMULTIPLE 011 3 ISNOTMULTIPLE 100 4 ISNOTMULTIPLE 000 0 ISMULTIPLE 001 1 ISNOTMULTIPLEExplanation / Answer
////////////// DESIGN FILE /////////////////////
module multiple_of_5 (
input [7:0] in1, // 8 bit input in BCD format
output reg [2:0] out1 // output
);
reg [3:0] temp;
// For a number to be multiple of 5 the last digit(LSB digit) is either 0 or 5
always @ (in1)
begin
temp = in1[4:0];
if ((temp == 4'd0) || (temp == 4'd5)) // if last digit is 0 or 5
out1 = 0;
else if (temp > 4'd5) // if last digit is greater than 5
out1 = temp - 4'd5;
else // if last digit is less than 5
out1 = temp[2:0];
end
endmodule
///////////// TEST_BENCH_FILE /////////////////
module multiple_of_5_tb;
reg [7:0] in1;
wire [2:0] out1;
reg [2:0] out1_with_mod;
integer i, j, dec_in;
// instantiation of the module
multiple_of_5 m1 (.in1(in1), .out1(out1));
initial
begin
$display (" INPUT OUT MOD_OUT RESULT");
// BCD input Generation
for(i = 0 ; i < 3 ; i = i + 1) begin
in1[7:4] = i;
for (j = 0; j < 10; j = j + 1 ) begin
in1[3:0] = j;
#20;
end
end
in1 = 8'h30; #20;
in1 = 8'h31; #20;
end
initial
begin
// output with modulus operator requires decimal input, so generating
// decimal input
for (dec_in = 0; dec_in < 32; dec_in = dec_in + 1) begin
out1_with_mod = dec_in % 5; #20;
end
end
always @ (out1)
begin
if (out1 == 3'd0)
$monitor("in1 = %b out1 = %b out1_with_mod = %d ISMULTIPLE", in1, out1, out1_with_mod );
else
$monitor("in1 = %b out1 = %b out1_with_mod = %d ISNOTMULTIPLE", in1, out1, out1_with_mod);
end
endmodule
/************* Simulation Result ********************
INPUT OUT MOD_OUT RESULT
in1 = 00000000 out1 = 000 out1_with_mod = 0 ISMULTIPLE
in1 = 00000001 out1 = 001 out1_with_mod = 1 ISNOTMULTIPLE
in1 = 00000010 out1 = 010 out1_with_mod = 2 ISNOTMULTIPLE
in1 = 00000011 out1 = 011 out1_with_mod = 3 ISNOTMULTIPLE
in1 = 00000100 out1 = 100 out1_with_mod = 4 ISNOTMULTIPLE
in1 = 00000101 out1 = 000 out1_with_mod = 0 ISMULTIPLE
in1 = 00000110 out1 = 001 out1_with_mod = 1 ISNOTMULTIPLE
in1 = 00000111 out1 = 010 out1_with_mod = 2 ISNOTMULTIPLE
in1 = 00001000 out1 = 011 out1_with_mod = 3 ISNOTMULTIPLE
in1 = 00001001 out1 = 100 out1_with_mod = 4 ISNOTMULTIPLE
in1 = 00010000 out1 = 000 out1_with_mod = 0 ISMULTIPLE
in1 = 00010001 out1 = 001 out1_with_mod = 1 ISNOTMULTIPLE
in1 = 00010010 out1 = 010 out1_with_mod = 2 ISNOTMULTIPLE
in1 = 00010011 out1 = 011 out1_with_mod = 3 ISNOTMULTIPLE
in1 = 00010100 out1 = 100 out1_with_mod = 4 ISNOTMULTIPLE
in1 = 00010101 out1 = 000 out1_with_mod = 0 ISMULTIPLE
in1 = 00010110 out1 = 001 out1_with_mod = 1 ISNOTMULTIPLE
in1 = 00010111 out1 = 010 out1_with_mod = 2 ISNOTMULTIPLE
in1 = 00011000 out1 = 011 out1_with_mod = 3 ISNOTMULTIPLE
in1 = 00011001 out1 = 100 out1_with_mod = 4 ISNOTMULTIPLE
in1 = 00100000 out1 = 000 out1_with_mod = 0 ISMULTIPLE
in1 = 00100001 out1 = 001 out1_with_mod = 1 ISNOTMULTIPLE
in1 = 00100010 out1 = 010 out1_with_mod = 2 ISNOTMULTIPLE
in1 = 00100011 out1 = 011 out1_with_mod = 3 ISNOTMULTIPLE
in1 = 00100100 out1 = 100 out1_with_mod = 4 ISNOTMULTIPLE
in1 = 00100101 out1 = 000 out1_with_mod = 0 ISMULTIPLE
in1 = 00100110 out1 = 001 out1_with_mod = 1 ISNOTMULTIPLE
in1 = 00100111 out1 = 010 out1_with_mod = 2 ISNOTMULTIPLE
in1 = 00101000 out1 = 011 out1_with_mod = 3 ISNOTMULTIPLE
in1 = 00101001 out1 = 100 out1_with_mod = 4 ISNOTMULTIPLE
in1 = 00110000 out1 = 000 out1_with_mod = 0 ISMULTIPLE
in1 = 00110001 out1 = 001 out1_with_mod = 1 ISNOTMULTIPLE
****************************************************/
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