Problem 5 (20 points) Recall that the combinational circuit to add two single-di
ID: 2249083 • Letter: P
Question
Problem 5 (20 points) Recall that the combinational circuit to add two single-digit BCD numbers. Note that when the sum exceeds it is "wrapped around" and a carry-out is generated. For example, the sum of 00 (8) ad -ol 01” (5) becomes-o011” (3) and carry-out becomes l . The input and output signals are BCD number format use 4 bits to encode digits 0 to 9. We want to design a .a, b:4-bit inputs in BCD format y: 4-bit output in BCD format . cout: carryout bit of BCD addition. The entity declaration is libzary ieee: use ieee.std logic 1164.all: use ieee.numeric std.all; entity bed adder is Porte a, b: in std_logic vector (3 downto 0) y: out std logic vector (3 downto o)i cout: out std logic end bed adder Derive the architecture body.Explanation / Answer
· Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bcd_adder is
port(
a,b : in unsigned(3 downto 0); -- input numbers.
carry_in : in std_logic;
sum : out unsigned(3 downto 0);
carry : out std_logic
);
end bcd_adder;
architecture arch of bcd_adder is
begin
process(a,b)
variable sum_temp : unsigned(4 downto 0);
begin
sum_temp := ('0' & a) + ('0' & b) + ("0000" & carry_in);
if(sum_temp > 9) then
carry <= '1';
sum <= resize((sum_temp + "00110"),4);
else
carry <= '0';
sum <= sum_temp(3 downto 0);
end if;
end process;
end arch;
If you see the code, there are three inputs. The 4 bit BCD digits 'a' and 'b'. The carry_in comes from the carry output from the neighboring adder(in the LSB side). For the first adder(which adds the least significant digits) carry_in is '0'.
I have used the following testbench code to test the design. The code is synthesizable and has been tested using Xilinx ISE 13.1. It should work with other tools as well.
Testbench code for the BCD adder:-
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_test IS
END tb_test;
ARCHITECTURE behavior OF tb_test IS
COMPONENT bcd_adder
PORT(
a : IN unsigned(3 downto 0);
b : IN unsigned(3 downto 0);
carry_in : in std_logic;
sum : OUT unsigned(3 downto 0);
carry : OUT std_logic
);
END COMPONENT;
signal a,b,sum : unsigned(3 downto 0) := (others => '0');
signal carry,carry_in : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bcd_adder PORT MAP (
a => a,
b => b,
carry_in => carry_in,
sum => sum,
carry => carry
);
-- Stimulus process
stim_proc: process
begin
a <= "1001"; b <= "1001"; carry_in <= '1'; wait for 100 ns;
a <= "1000"; b <= "1001"; wait for 100 ns;
a <= "0101"; b <= "1001"; wait for 100 ns;
a <= "0011"; b <= "1001"; wait for 100 ns;
a <= "1001"; b <= "0000"; carry_in <= '0'; wait for 100 ns;
a <= "1001"; b <= "0111"; wait for 100 ns;
a <= "0110"; b <= "0011"; wait for 100 ns;
wait;
end process;
END;