Instructions Desing a mod-16 asynchrous ripple up counter by using j-k flip-flop
ID: 2249439 • Letter: I
Question
Instructions Desing a mod-16 asynchrous ripple up counter by using j-k flip-flops. You need to design aj-k flip flop first and use it as the component in mod- 16 up counter design. Show both j-k flip-flop design implementation results and mod-16 up counter design implementation results. The report due date will be posted later. t. Note You will map the ‘clock, to a pushbutton switch so that you can generate the clock signal manually. This makes it easy to test that because the switch is not a real clock. Xilinx will produce an error. So in addition to the line (NET "clock" LOC xxxx), you need to include the following extra line in the constraints file: NET "clock" CLOCK DEDICATED ROUTE FALSEExplanation / Answer
PRESENT STATE
NEXT STATE
Q3
Q2
Q1
Q0
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Q0+
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Truth Table of JK Flip Flop
J
K
Q
Q’
0
0
No Change
0
1
0
1
1
0
1
0
1
1
Q’
Q
Hence for J=K=1, output toggles with every clock tick
First write behavioral description of JK Flip Flop
library ieee;
use ieee.std_logic_1164.all
entity jkff is
port(j, k, clk, rst: in std_logic;
q : out std_logic := ‘0’;
qbar : out std_logic := ‘1’);
end jkff;
architecture jkff_arch of jkff is
begin
process(clk, rst)
begin
if (rst = ‘1’) then --- asynchronous reset
q <= ‘0’; qbar <= ‘1’;
end if;
if falling_edge (clk) then --- negative edge
if (j = ‘0’ and k=’0’) then q <= q; qbar <= qbar; ----------- expression 1
elsif (j = ‘0’ and k=’1’) then q <= ‘0’; qbar <= ‘1’;
elsif (j = ‘1’ and k=’0’) then q <= ‘1’; qbar <= ‘0’;
elsif (j = ‘1’ and k=’1’) then q <= not q; qbar <= not qbar; --------- expression 2
end if;
end if;
end process;
end jkff_arch;
Normally to use JK Flip Flop as a counter, we operate it in a T Flip Flop mode where J = K = ‘1’. Now in this mode if you refer expression 1 and 2 from above code, the value of q and qbar depends on current status of q and qbar.
On hardware, a residual value available on q and qbar outputs helps in deciding next value of q and qbar.
Where as in simulation if there is no initial value on q and qbar then next value of q and qbar can’t be evaluated and hence we don’t see output during simulation.
To overcome this problem, we define some initial value on q and qbar during entity declaration using “:=” operator. Even if we reset the design in simulation by assigning rst =’1’ will solve the problem as q and qbar will get know state.
PRESENT STATE
NEXT STATE
Q3
Q2
Q1
Q0
Q3+
Q2+
Q1+
Q0+
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