I need verilog code for this question. Here is the Pin definition We have to pre
ID: 2249519 • Letter: I
Question
I need verilog code for this question.
Here is the Pin definition
We have to preload the counter with this value
Please help me write a Verilog code. If you need info regarding the DE10 LITE board please check the link below for the user manual
https://www.altera.com/content/dam/altera-www/global/en_US/portal/dsn/42/doc-us-dsnbk-42-2912030810549-de10-lite-user-manual.pdf
2 Counter In sequential circuits, counter is one of most widelv used function blocks They may be utilized to count the number of occurrences of the events generate control signa at the certain time, and so on. This is a group lab. 2.1 Specification In this lab, a pre-load increment counter is required to be designed and tested based upon DE10Lite FPGA board. A counter can be implemented by using if else or a FSM. The specifications of the counter are listed as below: Sy nchronized reset. The counter is activated by an enable signal 6 bits pre-load value set by 6 switches to determine the termination C) C) condition of the counter End-flag signal reflected through a LED. Pre-load value converted to the decimal number is mapped to 7 segments display. C) C) Interface is shown in Fig. 23Explanation / Answer
// sequential counter using Verilog
module counter( clk, count );
input clk;
output[3:0] count;
reg[3:0] count;
wire clk;
initial
count = 4'b0;
always @( negedge clk )
count[0] <= ~count[0];
always @( negedge count[0] )
count[1] <= ~count[1];
always @( negedge count[1] )
count[2] <= ~count[2];
always @( negedge count[2] )
count[3] <= ~count[3];
endmodule