Mechanism Reset Clk Design Problem 2 Write a VHDL code to design a register that
ID: 2249671 • Letter: M
Question
Mechanism Reset Clk Design Problem 2 Write a VHDL code to design a register that has 4-bit output, 4-bit D input, and 3-bit control- input S. All the changes of the output occur at the falling clock edge except for changes caused by Clear and Set which are asynchronous. The system operates as follows: Operation Hold state 001 Shift left 010 Shift Right 011 Asynchronous Clear 100 Asynchronous Set 101 Count Up 110 Count Down 1 Load You need to check what pin is used for the clock in the FPGA you are using. For example, on- campus students have to identify the FPGA chip used in the lab and check in its datasheet what pin corresponds to the clock. All students have to provide the code and snapshots of the pins assignment as well as the link to the datasheet that shows the FPGA pinouts for the clock (page needs to be specified). 13 PDFExplanation / Answer
Because the FPGA board you are going to work on is not specified the VHDL code doesnot include binding to clock, input and output signals. The code is well commented and is tested. (Only behavioral simulation) for all the cases. Hope it helps. All the best. Code starts from next line.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Shift_Reg is
Port ( clk : in STD_LOGIC; --Clock Input to the shift register
Q : out STD_LOGIC_VECTOR (3 downto 0); --Q (4 bit output)output of the shift register
D : in STD_LOGIC_VECTOR (3 downto 0); --D (4 bit input)input to the shift register
S : in STD_LOGIC_VECTOR (2 downto 0)); --S (3 bit input) select functoin input to the shift register
end Shift_Reg;
architecture Behavioral of Shift_Reg is
signal Qnext : STD_LOGIC_VECTOR (3 downto 0):= "0000"; --Signal to store next value of Q (4 bit signal)
signal Qpresent: STD_LOGIC_VECTOR (3 downto 0):= "0000";--Signal to store current value of Q (4 bit signal)
begin
update:process(clk,D,S) -- Process to update next output (Qnext)
begin
if(clk'event and clk = '1') then -- Check for rising clock edge for synchronous function
if(S = "000")then -- Hold the present output
Qnext <= Qpresent;
elsif (S = "001") then -- Left shift present output
Qnext <= Qpresent(2 downto 0)&"0";
elsif (S = "010") then -- Right shift present output
Qnext <= "0"&Qpresent(3 downto 1);
elsif (S = "101") then -- Increment present count by 1
Qnext <= Qpresent + 1;
elsif (S = "110") then -- Decrement present count by 1
Qnext <= Qpresent - 1;
elsif (S = "111") then -- Load input from D
Qnext <= D;
else
null; -- No action for any other input S
end if;
end if;
if (S = "011") then -- Asynchronous Clear for output Q
Qnext <= "0000";
elsif (S = "100") then -- Asyncronous Set for the output Q
Qnext <= "1111";
else
null;
end if;
end process update;
output: process(Qnext) -- Process to update the Output signal Q
begin
Q <= Qnext;
Qpresent <= Qnext; -- Current state = Qnext because output is Qnext
end process output;
end Behavioral;