Need help with this VHDL- Multiplexer (MUX) designs PART ONE: Design a 4-to-1 MU
ID: 2266050 • Letter: N
Question
Need help with this VHDL- Multiplexer (MUX) designs
PART ONE: Design a 4-to-1 MUX using only three 2-to-1 MUXes. Write an entity- architecture pair to implement a 2-to-1 MUX. Then write an entity-architecture pair to implement a 4-to-1 MUX using three instances of your 2-to-1 MUX.
(Hint: The equation for a 4-to-1 MUX can be rewritten as
F = A(I0*B + I1*B) + A(I2B + I3B).)
Use the following port definitions:
For the 2-to-1 MUX:
port (i0, i1: in bit; sel: in bit; z: out bit);
For the 4-to-1 MUX:
port (i0, i1, i2, i3: in bit; a, b: in bit; f: out bit);
PART 2: Simulate your code and test it using the following inputs:
I0 = I2 = 1, I1 = I3 = 0, AB = 00, 01, 11, 10
PART 3: Design your own 2-to-1 MUX in VHDL using www.edaplayground.com and use this MUX to implement a 4-to1 MUX. Note: your input and outputs should be of the type std_logic (not bit)
ALL CODE SHOULD BE EXECUTABLE using www.edaplayground.com
Apologize for the length
Explanation / Answer
Hey !!! I'm writing both the Verilog and VHDL code for this question.
VERILOG CODE:
//For 2x1 mux
module mux2_1(input i0,i1,sel,output z);
assign z= (~sel & i0) | (sel & i1);
endmodule
// For 4x1 mux using 2x1 mux
module mux4_1(input i0,i1,i2,i3,sel1,sel0, output f);
wire z0,z1;
//mux2_1 module instatiation
mux2_1 M1(i0,i1,sel0,z0);
mux2_1 M2(i1,i2,sel0,z1);
mux2_1 M3(z0,z1,sel1,f);
endmodule
VHDL CODE:
// FOR 2X1MUX
entity mux2_1 is
port(
i0,i1,sel : in STD_LOGIC;
z : out STD_LOGIC);
end mux2_1;
architecture Behavioral of mux2_1 is
begin
z<= ((not sel and i0) or (sel and i1));
end Behavioral
//FOR 4X1MUX
entity mux4_1 is
port (
i0,i1,i2,i3,sel0,sel1 : in STD_LOGIC;
f : out STD_LOGIC);
end mux4_1;
architecture Behavioral of mux4_1 is
component mux2_1 is
port( i0,i1,sel : in STD_LOGIC;
z : out STD_LOGIC);
end component;
signal y1,y2 : std_logic;
begin
m1: mux2_1 port map(i0=>i0, i1=>i1, sel=>sel0, z=>y1);
m2: mux2_1 port map(i0=>i2, i1=>i3, sel=>sel0, z=>y2);
m3: mux2_1 port map(i0=>y1, i1=>y2, sel=>sel1, z=>f);
end Behavioral
*** If you have Xilinx installed in your pc, you can run this code or you can go for edaplayground. I verified this code for Xilinx only.
*** One suggestion is try to understand the Verilog code and also learn Verilog as it'll help you a lot in your future. Remeber 99% industries only write RTLs using Verilog, not using VHDL.
Thanks