Problem 2 (16 pts.): Circle the correct answer No CorrectAnswer Question High 1
ID: 2266435 • Letter: P
Question
Problem 2 (16 pts.): Circle the correct answer No CorrectAnswer Question High 1 The impedance of an input node of a pseudo NMOS inverter is: 2In a self-aligned CMOS process, gate poly is Before After At the same time drain-source regions are deposited implanted 3 Dynamic power of a CMOS inverter has what Directly Inversely No relation relationship to the frequency of the applied proportional Proportional input 4 Compared to a 6-transistor static cell RAM, a Faster SlowerSame in 1-transistor dynamic cell RAM memory is speed generally In questions 5 to 10, put a check mark in front of those logies which are pot ratio-less 5 NMOS PTL (pass transistor logic): 6 PMOS PTL (pass transistor logic): 7 TGL (transmission gate logic): 8 CMOS logic: 9 Dynamic logic: 10 Pseudo NMOS logic: In questions 11 to 16, put a check mark()irn front of those logics which are not rail-to-rail. 11 NMOS PTL (pass transistor logic): 12 PMOS PTL (pass transistor logic): 13 TGL (transmission gate logic): 14 CMOS logic: 15 Dynamic logic: 16 Pseudo NMOS logic:Explanation / Answer
Answer
1. The impedance of an input node of a pseudo-NMOS inverter is High
2. In a self-aligned CMOS process, gate poly is deposited before drain-source regions are implanted Before
3. Dynamic power = n* C * f* Vdd^2 Directly Proportional
4. SRAM cell is faster than DRAM memory cell Slower