Assignment 1 Notes: .Submission MUST be only 1 PDF or Doc format document of oyp
ID: 2267446 • Letter: A
Question
Assignment 1 Notes: .Submission MUST be only 1 PDF or Doc format document of oyped report. (For example, hand written scanned file is not acceptable) Do not upload a zip file containing multiple files Only 1 file can be uploaded (any new upload will replace the old upload). The deadline is timed, and will stop accepting new upload at 11:59pm on the designated date. In the report, clearly mention the type of HDL code (ie. Verilog, VHDL, or System Verilog) that you have used for solution of these problems. Use only one for your entire report. 1. a) Write an 16:1 multiplexer module called muax16 with inputs So, din, and output y. Data input (din) and data output (y) are 32-bit wide. b) Write a testbench to functionally verify your code in part a. 2. a) Write an HDL code for a 4-bit Gray code counter. b) Write a testbench to functionally verify your code in part a.Explanation / Answer
HDL used is Verilog
1. Verilog Code for 16:1 mux
module mux16(din, s, y);
input [32:0] din [15:0];
input [3:0] s;
output [32:0] y;
reg y;
always @(din or s)
begin
case (s)
4’b0000:y=din[0];
4’b0001:y=din[1];
4’b0010:y=din[2];
4’b0011:y=din[3];
4’b0100:y=din[4];
4’b0101:y=din[5];
4’b0110:y=din[6];
4’b0111:y=din[7];
4’b1000:y=din[8];
4’b1001:y=din[9];
4’b1010:y=din[10];
4’b1011:y=din[11];
4’b1100:y=din[12];
4’b1101:y=din[13];
4’b1110:y=din[14];
4’b1111:y=din[15];
default:y=0;
endcase
end
endmodule
MUX test Bench
module muxtb;
reg [32:0] din [15:0];;
reg [3:0] s;
wire [32:0]y;
mux16 m1(din,s,y);
initial
begin
#20 din[0]=4’b1010000000000000;
#20 s=4’b0000;
#20 din[1]=4’b1010000010000001;
#20 s=4’b0001;
#20 din[2]=4’b1010000001100011;
#20 s=4’b0010;
#20 din[2]=4’b1010011000000011;
#20 s=4’b0011;
#20 din[2]=4’b1010000001010011;
#20 s=4’b0100;
#20 din[2]=4’b1011110000000011;
#20 s=4’b0101;
#20 din[2]=4’b1111000000000011;
#20 s=4’b0110;
#20 din[2]=4’b1110000000000011;
#20 s=4’b0111;
#20 din[2]=4’b1010000000001111;
#20 s=4’b1000;
#20 din[2]=4’b1010000000000011;
#20 s=4’b1001;
#20 din[2]=4’b1010000000011111;
#20 s=4’b1010;
#20 din[2]=4’b1010000000000011;
#20 s=4’b1011;
#20 din[2]=4’b1011111000000011;
#20 s=4’b1100;
#20 din[2]=4’b1010011100000011;
#20 s=4’b1101;
#20 din[2]=4’b1010011111000011;
#20 s=4’b1110;
#20 din[2]=4’b1010000001111111;
#20 s=4’b1111;
#20 din[2]=4’b111111111111111;
#20 $stop;
end
endmodule
2.Verilog code for gray counter
module graycount(clock, reset, out);
input clock, reset;
output reg [3:0] out;
reg q0, q1, q2;
reg [3:0] count;
always @ (posedge clock)
begin
if (reset)
count = 4'b0;
out = 4'b0;
else
count = count + 1'b1;
q2 = count[3] ^ count[2];
q1 = count[2] ^ count[1];
q0 = count[1] ^ count[0];
out = {count[3], q2, q1, q0};
end
endmodule
Test bench for gray counter
module graytest;
reg clock,reset
wire [3:0] out;
gray g1(clock,reset,out);
initial
clock = 1’b0;
always
#5 clock = ~clock;
initial
begin
reset = 1’b1;
#15 reset = 1’ b0 ;
#100 reset = 1’b1;
#20 finish;
endmodule