Create a Verilog module that sets values for Q below based on x and W, this can
ID: 2267762 • Letter: C
Question
Create a Verilog module that sets values for Q below based on x and W, this can be done with an always and case statement. For all cases not given set Q to 3'bo00 (use this for your default value, you must include a default in your solution), but do this with minimum code. Module inputs are x and W, output is Q. W and Q are 3 bits wide as shown in the table. Start with a module statement defining the ports and end with an endmodule. The module name should be case_ ex. Your code must be written with correct syntax so that it would compile,link, and synthesize correctly. 001 010 02 010 001 0 0) 010Explanation / Answer
module case_ex (x, W, Q);
input x;
input [2:0] W;
output reg [2:0] Q;
always @ (*)
begin
case ({x,W})
4'b0001 : Q = 3'b010;
4'b0010 : Q = 3'b001;
4'b1100 : Q = 3'b100;
4'b1111 : Q = 3'b010;
default : Q = 3'b000;
endcase
end
endmodule