Please solve this question. Thanks, Design a VHDL module for the following state
ID: 2268004 • Letter: P
Question
Please solve this question. Thanks,
Design a VHDL module for the following state machine that will be used to control a vending machine 25c 10c return 25c return 10c return 5c Coin Sensor Return State Machine clk reset vend Soft Drinks Assumptions Clock speed is 100 MHz * Reset is active high and must set the state machine in an idle state . The vending machine only takes quarters, dimes, and nickels . The vending machine only returns quarters, dimes, and nickels . Each input (25c, 1Oc, 5c) is a one clock cycle wide pulse that is synchronous with the clock signal * Inputs will occur "one at a time". You will not ever have 2 or more inputs asserted on the same clock cycle . To dispense change, assert each output (return-25c, return-10c, and return-5c) for one clock cycle . Each beverage in the machine costs $0.25 * The supply of coins for change and beverages is unlimited . The vend signal should only be asserted for one clock cycle when the user has inserted at least $0.25Explanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vend_mach is
port( Clk : in std_logic;
x,y : out std_logic;
i,j : in std_logic
);
end vend_mach;
architecture Behavioral of vend_mach is
--type of state machine and signal declaration.
type state_type is (a,b,c);
signal next_s : state_type;
begin
process(Clk)
begin
if(rising_edge(Clk)) then
case next_s is
when a =>
if(i='0' and j='0') then
x <= '0';
y <= '0';
next_s <= a;
elsif(i='1' and j='0') then
x <= '0';
y <= '0';
next_s <= b;
elsif(i='1' and j='1') then
x <= '0';
y <= '0';
next_s <= c;
end if;
when b =>
if(i='0' and j='0') then
x <= '0';
y <= '0';
next_s <= b;
elsif(i='1' and j='0') then
x <= '0';
y <= '0';
next_s <= c;
elsif(i='1' and j='1') then
x <= '1';
y <= '0';
next_s <= a;
end if;
when c =>
if(i='0' and j='0') then
x <= '0';
y <= '0';
next_s <= c;
elsif(i='1' and j='0') then
x <= '1';
y <= '0';
next_s <= a;
elsif(i='1' and j='1') then
x <= '1';
y <= '1';
next_s <= a;
end if;
end case;
end if;
end process;
end Behavioral;
another method
library ieee;
use IEEE.std_logic_1164.all;
entity FSM is
port (CLK : in std_logic; --Clock, active high
RSTn : in std_logic; --Async. Reset, active low
CoinIn : in std_logic_vector (1 downto 0); --Which coin was inserted
Soda : out std_logic; --Is Soda dispensed ?
CoinOut : out std_logic_vector (1 downto 0) --Which coin is dispensed?
);
end entity;
architecture behavior of FSM is
-- add your code here
type state_type is (idle, --start state/reset
put_money, --waiting to enter money
in_1,in_3,in_6,in_5, --represent the current sum of money after returning change
change_1, --should return change of 1$
soda_out --dispence soda can.
); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
begin
process(CLK,RSTn)
begin
if(RSTn = '0') then
current_s <= idle; --defualt state is on RESET
elsif(clk'event and clk = '1') then
current_s <= next_s;
end if;
end process;
--------------------
--FSM process:
process(current_s,CoinIn)
begin
case current_s is
when idle => --state reset or idle
Soda <= '0';
CoinOut <= "00";
next_s <= put_money;
------------------------------------------------------
when put_money => --wait for money to be entered
if(CoinIn = "00")then
Soda <= '0';
CoinOut <= "00";
next_s <= put_money;
elsif(CoinIn = "01")then --insert 1$
Soda <= '0';
CoinOut <= "00";
next_s <= in_1;
elsif(CoinIn = "10")then --insert 2$
Soda <= '0';
CoinOut <= "00";
next_s <= soda_out;
elsif(CoinIn = "11")then --insert 5$
Soda <= '0';
CoinOut <= "00";
next_s <= in_5;
end if;
------------------------------------------------------
when in_1 =>
if(CoinIn = "00") then--stay on the same state
Soda <= '0';
CoinOut <= "00";
next_s <= in_1;
elsif(CoinIn = "01") then--inserted another 1$
Soda <= '0';
CoinOut <= "00";
next_s <= soda_out;
elsif(CoinIn = "10") then--inserted another 2$
Soda <= '0';
CoinOut <= "00";
next_s <= in_3;
elsif(CoinIn = "11") then
Soda <= '0';
CoinOut <= "10";
next_s <= in_6;
end if;
------------------------------------------------------
when in_3 =>
Soda <= '0';
CoinOut <= "01";
next_s <= soda_out;
------------------------------------------------------
when in_6 =>
Soda <= '0';
CoinOut <= "01";
next_s <= in_5;
------------------------------------------------------
when in_5 => -- input = 5 coin
Soda <= '0';
CoinOut <= "10";
next_s <= change_1;
------------------------------------------------------
when change_1 => -- input = 5 coin
Soda <= '0';
CoinOut <= "01";
next_s <= soda_out;
------------------------------------------------------
when soda_out =>
Soda <= '1';
CoinOut <= "00";
next_s <= put_money;
end case;
end process;
end behavior;