Student Name Ouestion 4: VHDL (10 marks) Consider a logic operator that can be e
ID: 2268439 • Letter: S
Question
Student Name Ouestion 4: VHDL (10 marks) Consider a logic operator that can be either a buffer or an inverter. If a mode select line called MODE_CNTRL is set to '0', then the output SIG_OUT equals the inverse of the input SIG_IN. If MODE_CNTRL is set to '1', then the output SIG_OUT equals the input SIG IN. a) Write a complete VHDL description using concurrent signal assignments of your choice. Rewrite the VHDL code. This time, create components describing a buffer, an b) inverter, and other needed hardware elements. Then write the complete description using your components.Explanation / Answer
VHDL Concurrent Conditional Assignment
The Conditional Signal Assignment statement is concurrent because it is assigned in the concurrent section of the architecture. It is possible to implement the same code in a sequential version, as we will see next.
The conditional signal assignment statement is a process that assigns values to a signal.
It is a concurrent statement; this means that you must use it only in concurrent code sections.
The statement that performs the same operation in a sequential environment is the “if” statement.
The syntax for a conditional signal assignment statement is:
a <= b when c=’1’ else d;
architecture Structure of Decoder_bcd is
signal S: Bit_Vector(0 to 1);
component AND_Gate
port(A,B:in Bit; D:out Bit);
end component;
component Inverter
port(A:in Bit; B:out Bit);
end component;
begin
Inv1:Inverter port map(A=>bcd(0), B=>S(0));
Inv2:Inverter port map(A=>bcd(1), B=>S(1));
A1:AND_Gate port map(A=>bcd(0), B=>bcd(1), D=>led(3));
A2:AND_Gate port map(A=>bcd(0), B=>S(1), D=>led(2));
A3:AND_Gate port map(A=>S(0), B=>bcd(1), D=>led(1));
A4:AND_Gate port map(A=>S(0), B=>S(1), D=>led(0));
end Structure;
The components Inverter and AND_Gate are instantiated under the names Inv1, Inv2, A1, A2, A3 and A4. The connections among the components are realized by the use of signals S(0), S(1) declared in the architecture's declarative part.