Problem 5 (20 points): Circle the right answer. i) A register that contains that
ID: 2291658 • Letter: P
Question
Problem 5 (20 points): Circle the right answer. i) A register that contains that address of the current instruction a) PC b) AC MDR MAR e ALU ii) Within the VHDL code for a device, where would the statement "PORT(A,B.C IN STD LOGIC): be found? a) Under the "ENTITY Under a "CASE c) Under the "ARCHITECTURE d) Under a "PROCESS" e) After a "USE iii) In Lab 3, an appendix provided information about "propagating values" and "controlling values," which were used to set up test conditions for measuring your worst-case propagation delay. What is the controlling value for an OR gate (the value on one input that controls the output, independent of the other input)? a) 0 b) 1 c) High-impedance d) None of the above iv)PROCESS (reset, clock) BEGIN IF reset- 'I' THEN ELSIF ( clock 'EVENT AND clock = V' ) THEN END IF: END PROCESS The VHDL code above could best be described as a) A positive-edge triggered D flip-flop with an active-high reset b) A negative-edge triggered D flip-flop with an active-high reset e) A positive-edge triggered D flip-flop with an active-low reset d) A negative-edge triggered D flip-flop with an active-low resetExplanation / Answer
Solutions :
1) The Program counter is the register which contains the address of current instruction
2) The code PORT(A, B, C : IN STD_LOGIC); is found under Enity which declares all the input and output ports of the module
4)
PROCESS (reset, clock) -- asynchronous reset
BEGIN
IF reset = '1' THEN -- active high
Q3 <= '0';
ELSIF (clock'event AND clock = '0' ) THEN -- NEgative edge
Q3 <= 'D';
END IF;
END PROCESS;
The above code infers a "Negative edge D Flip Flop with an Asunchronous active high reset"