Consider the following program and cache behaviors. Data Reads per Data Writes p
ID: 2291688 • Letter: C
Question
Consider the following program and cache behaviors. Data Reads per Data Writes per Instruction Cache Data Cache Block Size 1000 Instructions 1000 Instructions Miss Rate Miss Rate (byte) 250 100 03% 2% 64 5.4.4 [5] For a write-through, write-allocate cache, what are the minimum read and write bandwidths (measured by byte per cycle) needed to achieve a CPI of 2? 5.4.5 [5] For a write-back, write-allocate cache, assuming 30% of replaced data cache blocks are dirty, what are the minimal read and write bandwidths needed for a CPI of 2? 5.4.6 [5] What are the minimal bandwidths needed to achieve the performance of CPI-1.5?Explanation / Answer
5.4.6 can be answered in the following way (The method is simiar to 5.4.5)
Dirty cache read miss penalty = I × 0.25 × 0.02 × (1 + 0.3) × (64/W + 1)
Dirty cache write miss penalty = I × 0.1 × 0.02 × (1 + 0.3) × (64/W + 1)
read miss penalty = I × 0.003 × (64/ W + 1)
Total execution time = hit time + miss penalty
Therefore,
Total execution time = I + I × [0.25 × 0.02 × 1.3 + 0.1 × 0.02 × 1.3 + 0.003] × (64/W + 1) ? 1.5I
Which can be written as
0.0121 × (64/W + 1) ? 0.5
Hence W ? 1.587 Bytes/cycle