Create a basic floating point multiplication algroithm in verilog. Underflow/ove
ID: 2292759 • Letter: C
Question
Create a basic floating point multiplication algroithm in verilog. Underflow/overflow not needed.
Basic Floating Point Multiplication Algorithm Assuming that the operands are already in the IEEE 754 Single Precision format performing floating point multiplication: Result = R-X * Y = (-1)xs (Xm x 2x*) * (-1)""(Ym x 2m involves the following steps: a) rean ar buth aperarmer (2) Compute the sign of the result Xs XOR Ys (3) Compute the mantissa of the result: . Multiply the mantissas Xm * Ym Round the result to the allowed number of mantissa bits . Rounding strategy: round towards zero (4) Compute the exponent of the result: (5) Normalize if needed, by shifting mantissa right, incrementing result exponent. If you can finish steps (1) to (5), you get full credit of 100. (6) Check result exponent for overflow/underflow Result exponent = biased exponent (X) + biased exponent (Y) -bias I larer than maximum exponent allowed return exponent overflow If smaller than minimum exponent allowed return exponent underflow If you can also finsih step (6), you'll get extra bonus. For your implementation of overflow: you'll get 5 point extra bonus For your implementation of underflow: you'll get 5 point extra bonus So, if you can finish both underflow and overflow design, you'll get 10 point extra bonusExplanation / Answer
Basic floating point multiplication algroithm in verilog
module fp32_multi(X,Y,R);
input [31:0] X,Y; output [31:0] R;
xor (R[31],X[31],Y[31]);
assign R[30:23]= X[30:23]+Y[30:23]-7'b1111111;
wire [51:0] mult;
wire [25:0] mp,md;
assign mp={3'b001,X[22:0]};
assign md={3'b001,Y[22:0]};
radix4_modul_mux b1(mult,mp,md);
assign R[22:0]=mult[45:23];
endmodule
module radix4_modul_mux(mult,ain,bin);
input [25:0] ain,bin; output [51:0] mult;
wire [51:0] encode,pp1,pp2,pp3,pp4,pp5,pp6,pp7,pp8,pp9,pp10,pp11,pp12,pp13;
assign encode={{26{ain[25]}},ain};
ppx p1(pp1,encode,{bin[1:0],1'b0});
ppx p2(pp2,encode,bin[3:1]);
ppx p3(pp3,encode,bin[5:3]);
ppx p4(pp4,encode,bin[7:5]);
ppx p5(pp5,encode,bin[9:7]);
ppx p6(pp6,encode,bin[11:9]);
ppx p7(pp7,encode,bin[13:11]);
ppx p8(pp8,encode,bin[15:13]);
ppx p9(pp9,encode,bin[17:15]);
ppx p10(pp10,encode,bin[19:17]);
ppx p11(pp11,encode,bin[21:19]);
ppx p12(pp12,encode,bin[23:21]);ppx p13(pp13,encode,bin[25:23]);
assign mult=pp1+(pp2<<2)+(pp3<<4)+(pp4<<6)+(pp5<<8)+(pp6<<10)+(pp7<<12)+(pp8<<14)
+(pp9<<16)+(pp10<<18)+(pp11<<20)+(pp12<<22)+(pp13<<24);
endmodule
module ppx (ppg,i,s);
input [2:0] s;
input [51:0] i;
output [51:0] ppg;
assign ppg=(i&(({52{~s[2]}}&{52{~s[1]}}&{52{s[0]}})
|({52{~s[2]}}&{52{s[1]}}&{52{~s[0]}})))
|((i<<1)&({52{~s[2]}}&{52{s[1]}}&{52{s[0]}}))
|((-(i<<1))&({52{s[2]}}&{52{~s[1]}}&{52{~s[0]}}))
|((-i)&(({52{s[2]}}&{52{~s[1]}}&{52{s[0]}})|({52{s[2]}}&{52{s[1]}}&{52{~s[0]}})))
;
endmodule