Please solve 6.2.3 part Complete the below state table output column, noting tha
ID: 2315471 • Letter: P
Question
Please solve 6.2.3 part
Complete the below state table output column, noting that the output is the state number decoded to be displayed on a 7-Segment LED Display (DP bit is not used). Draw a state diagram that corresponds to the state table. Is this a Mealy machine? Show the transition table corresponding to the state table using one-hot encoding for the state assignments. (Do not try to reduce the number of states.) How many D Flip-Flops would you need to store the state with this encoding scheme? A property of one-hot state assignment is the simplicity of the flip-flop input logic. Draw a logic schematic for the one-hot FSM using D Flip-Flops after deriving the input equations directly using the transition table from 6.2.2 (without using K-maps). Add the decoding logic to your schematic showing an implementation for the 7-Segment Output. Following the behavioral description example provided in Section 6.3, write up a VHDL code for the above FM with one-hot state assignment. Do not forget to include the implementation of the 7-Segment Output decoding logic in the same code. Submit a printout of your VHDL code. It is a good idea for you to bring along a USB flash memory containing your code, and also save all of your lab work to it. Your work from this lab will be useful in the final project.Explanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is
port (
clk : in std_logic;
bcd : in std_logic_vector(3 downto 0); --BCD input
segment7 : out std_logic_vector(6 downto 0) -- 7 bit decoded output.
);
end test;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of test is
begin
process (clk,bcd)
BEGIN
if (clk'event and clk='1') then
case bcd is
when "0000"=> segment7 <="0000001"; -- '0'
when "0001"=> segment7 <="1001111"; -- '1'
when "0010"=> segment7 <="0010010"; -- '2'
when "0011"=> segment7 <="0000110"; -- '3'
when "0100"=> segment7 <="1001100"; -- '4'
when "0101"=> segment7 <="0100100"; -- '5'
when "0110"=> segment7 <="0100000"; -- '6'
when "0111"=> segment7 <="0001111"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0000100"; -- '9'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end if;
end process;
end Behavioral;
If you want a decimal number to be displayed using this code then convert the corresponding code into BCD and then instantiate this module for each digit of the BCD code.
Here is a sample test bench code for this module:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
ENTITY test_tb IS
END test_tb;
ARCHITECTURE behavior OF test_tb IS
signal clk : std_logic := '0';
signal bcd : std_logic_vector(3 downto 0) := (others => '0');
signal segment7 : std_logic_vector(6 downto 0);
constant clk_period : time := 1 ns;
BEGIN
uut: entity work.test PORT MAP (clk,bcd,segment7);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: process
begin
for i in 0 to 9 loop
bcd <= conv_std_logic_vector(i,4);
wait for 2 ns;
end loop;
end process;
END;