Please tell me what is wrong with this VHDL. Why is it expexting an \"if\" when
ID: 2317785 • Letter: P
Question
Please tell me what is wrong with this VHDL. Why is it expexting an "if" when I am trying to end it?
I am getting this error;
Error (10500): VHDL syntax error at homewk4_9.vhd(22) near text "PROCESS"; expecting "if"
ENTITY homewk4_7 IS
PORT(
CLOCK :IN BIT;
CLR :IN BIT;
QOUT :BUFFER INTEGER RANGE 0 TO 7);
END homewk4_7;
ARCHITECTURE behavior OF homewk4_7 IS
BEGIN
PROCESS(CLOCK, CLR)
BEGIN
IF(CLR = '0') THEN
QOUT <= 0;
ELSE IF(CLOCK'EVENT AND CLOCK = '1') THEN
IF QOUT = 0 THEN QOUT <= 1;
ELSE IF QOUT = 1 THEN QOUT <= 2;
ELSE IF QOUT = 2 THEN QOUT <= 6;
ELSE IF QOUT = 6 THEN QOUT <= 7;
ELSE IF QOUT = 7 THEN QOUT <= 0;
END IF;
END IF;
END PROCESS;
END behavior;
Explanation / Answer
ENTITY homewk4_7 IS
PORT(
CLOCK :IN BIT;
CLR :IN BIT;
QOUT :BUFFER INTEGER RANGE 0 TO 7);
END homewk4_7;
ARCHITECTURE behavior OF homewk4_7 IS
BEGIN
PROCESS(CLOCK, CLR)
BEGIN
IF(CLR = '0') THEN
QOUT <= 0;
ELSE IF(CLOCK'EVENT AND CLOCK = '1') THEN
IF QOUT = 0 THEN QOUT <= 1;
ELSE IF QOUT = 1 THEN QOUT <= 2;
ELSE IF QOUT = 2 THEN QOUT <= 6;
ELSE IF QOUT = 6 THEN QOUT <= 7;
ELSE QOUT = 7 THEN QOUT <= 0; %if elseif statement should contain else statement at the last condition
END IF;
END IF;
END PROCESS;
END behavior;