Create a 8 bit subtractor in Verilog that uses a 8-bit adder. Write a test bench
ID: 2318566 • Letter: C
Question
Create a 8 bit subtractor in Verilog that uses a 8-bit adder. Write a test bench that will test the code with 2 sets of numbers made up of the ASCII Values of the first 2 letters of your first name and the first 2 letters of your last name as the 2 sets of 8 bit numbers. In each case subtract the 1^st letter from the second letter in the test bench and use the $display command to print the results and paste in a screen shot and the code. Write Verilog code for a module called JKff (JK Flip Flop) that has inputs J.K, ClrN, SctN, Clk and outputs Q and QN. Make the ClrN asynchronous. Write a test bench to simulate all combinations of J and K for the single FF. Then create a module that uses 4 instantiations of the JKff to create a register that can hold 4 bits, but do not write test bench for the 4 bits. Submit code and test bench code.Explanation / Answer
1)8bit subtraactor code;
module subtractor_8bit(
input [7:0] A,
input [7:0] B,
output [7:0] Difference,
output Borrow
);
Adder8 s1(A,B,"1",Difference,Borrow);
endmodule
module Adder8(
input [7:0] a,
input [7:0] b,
input cin,
output [7:0] s,
output cout
);
wire c2,c3,c4,c5,c6,c7,c8;
fa m1(s[0],c2,a[0],b[0],cin);
fa m2(s[1],c3,a[1],b[1],c2);
fa m3(s[2],c4,a[2],b[2],c3);
fa m4(s[3],c5,a[3],b[3],c4);
fa m5(s[4],c6,a[0],b[0],c5);
fa m6(s[5],c7,a[1],b[1],c6);
fa m7(s[6],c8,a[2],b[2],c7);
fa m8(s[7],cout,a[3],b[3],c8);
endmodule
module fa(s,cout,a,b,cin);
input a,b,cin;
output s,cout;
wire w1,w2,w3;
ha m1(w1,w2,a,b);
ha m2(s,w3,w1,cin);
or m3(cout,w2,w3);
endmodule
module ha(s,cout,a,b); //sub module for Half adder
input a,b;
output s,cout;
xor m1(s,a,b);
and m2(cout,a,b);
endmodule