Please solve question 10.N below, I am especially stuck on part b. I don\'t need
ID: 2990094 • Letter: P
Question
Please solve question 10.N below, I am especially stuck on part b.
I don't need you to do VHDL code nor really worry about solving part a, I need you to help me design the 8-to-3 priority encoder using the specficiations in part b.
Show your work.
Don't forget the enable input.
Design a 4-to-2 priority encoder with an enable input, using gates. (See Unit 9, Study Guide Part 4(b)). When enable is 0, all outputs are 0. Write a VHDL module for the encoder. Use the following port declaration: Port (y: in std _ logic _vector(0 to 3); enable: in std _logic; a1, b1, c1 : out std _logic); Design an 8-to-3 priority encoder (Figure 9-16) with an enable input, using two of the 4-to-2 priority encoders you designed in (a), three OR gates, an AND gate, and one inverter. Then write a VHDL module for this encoder. Use the port declaration: Port (y: in std _logic _vector(0 to 7); main _enable : in std _logic; a, b, c, d : out std _logic);Explanation / Answer
illustrates the debounce circuit in question. The circuit continuously clocks the button