Can someone create a test bench for this code in vhdl(please type it out). libra
ID: 3348985 • Letter: C
Question
Can someone create a test bench for this code in vhdl(please type it out).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity USR_4Bit is
port( LR,SP,clk,clear,shL,shR: in std_logic; -- shL = shift left shR= shift right
Da,Db,Dc: in std_logic; --inputs for load
Qa,Qb,Qc: out std_logic); --outputs from the flipflops
end USR_4Bit;
architecture Structural of USR_4Bit is
signal lr1,lr2,sp1,sp2,R1,R2,R3: std_logic;
signal L1,L2,L3,LOAD1,LOAD2,LOAD3:std_logic;
signal c1,c2,c3 : std_logic;
signal Qas,Qbs,Qcs : std_logic;
component andgate
port(a,b,c : in std_logic; z : out std_logic);
end component;
component orgate
port(a,b,c : in std_logic; z : out std_logic);
end component;
component notgate
port(a: in std_logic; z : out std_logic);
end component;
component Dflipflop
port(D,clk: in std_logic; Q: out std_logic);
end component;
begin
NOTG1: notgate port map (LR,lr1);--1st notgate for LEFT/RIGHT
NOTG2: notgate port map (lr1,lr2);--2nd notgate for LEFT/RIGHT
NOTG3: notgate port map (SP,sp1);--1st notgate for SERIAL/PARRALLEL
NOTG4: notgate port map (sp1,sp2);--2nd notgate for SERIAL/PARRALLEL
ANDG1: andgate port map (shR,sp2,lr2,R1); --right shift of 1st bit
ANDG2: andgate port map (sp2,lr1,Qbs,L1); --left shift of 1st bit
ANDG3: andgate port map (lr2,sp1,Da,LOAD1);--load of 1st bit
ANDG4: andgate port map (Qas,sp2,lr2,R2); --right shift of 2nd bit
ANDG5: andgate port map (sp2,lr1,Qcs,L2); --left shift of 2nd bit
ANDG6: andgate port map (lr2,sp1,Db,LOAD2);--load of 2nd bit
ANDG7: andgate port map (Qbs,sp2,lr2,R3); --right 3rd bit
ANDG8: andgate port map (sp2,lr1,shL,L3); --left 3rd bit
ANDG9: andgate port map (lr2,sp1,Dc,LOAD3);--loading 3rd bit
ORG1: orgate port map (R1,L1,LOAD1,c1);--for the 1st flipflop
ORG2: orgate port map (R2,L2,LOAD2,c2);--for the 2nd flipflop
ORG3: orgate port map (R3,L3,LOAD3,c3);--for the 3rd flipflop
FF1: Dflipflop port map (c1,clk,Qas);--FlipFlop = FF
FF2: Dflipflop port map (c2,clk,Qbs);
FF3: Dflipflop port map (c3,clk,Qcs);
process(clk,clear)
begin
if clear ='1' then
Qas<='0';
elsif (clk'event and clk = '1') then
Qas<=Qas;
Qa <= Qas;
end if;
end process;
process(clk,clear)
begin
if clear ='1' then
Qbs<='0';
elsif (clk'event and clk = '1') then
Qbs<= Qbs;
Qb <= Qbs;
end if;
end process;
process(clk,clear)
begin
if clear ='1' then
Qcs<='0';
elsif (clk'event and clk = '1') then
Qcs<=Qcs;
Qc <= Qcs;
end if;
end process;
end Structural;
Explanation / Answer
//Shift Left operation
//Shift Left operation
//Shift Left operation
//Again Load the datat
//Shift Right operation
//Shift Right operation
//Shift Right operation