Please solve it on VHDL code. Thanks, Partl Design Create a top level VHDL file
ID: 3349079 • Letter: P
Question
Please solve it on VHDL code. Thanks,
Partl Design Create a top level VHDL file that includes the following UART Transmitter shown in the diagra below. Your design should be implemented in a single VHDL file Each block shown in blue should be implemented as a separate VHDL process. o The state machine should be implemeted as three separate VHDL processes [state register next state logic, output forming logic). The ROM should contain 16 bytes (ADDR BITS 4, DATA BITS:8). Design the BAUD RATE GENERATOR (counter) for a rate of 115,200 Baud. When the counter reaches its terminal count, it should automaticaly roll over to a value of zero and continue counting. Please choose a 16-byte message you want to transmit, and then implement the ROM with VHDL, like the approach you used for Homework#6 Your design should have two outputs (UART Tx OUT and PMOD OUT) Expected Operation Wait for the user to press Button1. Next, the STATE MACHINE should reset the ADDRESS COUNTER Next, reset the BAUD RATE COUNTER and transmit the start bit by setting the MUX output to zero Once the BAUD RATE COUNTER reaches its terminal count, the state machine should assert LOAD to load the 8-bit DATA OUT value into the SHIFT REGISTER in parallel. The state machine should set the MUX to drive the 1-bit output of the SHIFT REGISTER to the serial autput pin L. 2. 3. 4. 5. Each time the counter rolls over; the STATE MACHINE should advance the SHIFT REGISTER by 6. Finally, the STATE MACHINE should transmit the stop bit by setting the MUX output to one for a 7. Next, the STATE MACHINE should increment the ADDRESS COUNTER to read the next memory 8. Repeat steps 3-7 until all 16 bytes stared in ROMve been transmitted asserting the SHIFT signal. Continue shifting data to the serial port for all eight bits. duration of one bit time lotation in the ROM 9. Return to step 1. EHIFT RLGISTER TRANSM1IT STARTExplanation / Answer
// let's assume the FPGA clock signal runs at 1.8432MHz
// we create a 4-bit counter
reg [3:0] BaudDivCnt;
always @(posedge clk) BaudDivCnt <= BaudDivCnt + 1; // count forever from 0 to 15
// and a tick signal that is asserted once every 16 clocks (so 115200 times a second)
wire BaudTick = (BaudDivCnt==15);
while(1) // repeat forever
{
acc += 115200;
if(acc>=2000000) printf("*"); else printf(" ");
acc %= 2000000;
}
parameter ClkFrequency = 25000000; // 25MHz
parameter Baud = 115200;
parameter BaudGeneratorAccWidth = 16;
parameter BaudGeneratorInc = (Baud<<BaudGeneratorAccWidth)/ClkFrequency;
reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
always @(posedge clk)
BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;
wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
parameter BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);