Convert the following code using variables rather than signals. Comment on the d
ID: 3349295 • Letter: C
Question
Convert the following code using variables rather than signals. Comment on the differences of a code that uses only signals to a code which makes use of variables.
entity converter is
port( sign_mag : in std_logic_vector(3 downto 0) ;
twos_comp : out std_logic_vector(3 downto 0) );
end converter;
architecture converter_arch of converter is
signal neg : std_logic_vector(3 downto 0);
begin
process(sign_mag)
begin
if (sign_mag <= 1000) then
twos_comp<=sign_mag;
else
neg <=('1' & not sign_mag(2 downto 0))+1;
twos_comp<=neg;
end if;
Explanation / Answer
// variable assign values immediately but signal assigned after delta delay
entity converter is //Entity converter is decleared
port( sign_mag : in std_logic_vector(3 downto 0) ; //Input is assigned as std logiicvecot hving width of 3
twos_comp : out std_logic_vector(3 downto 0) ); //Similarly outputis declared
end converter; //Endof entity
architecture converter_arch of converter is
begin
process(sign_mag) // process assigned with senstivity element sign_mag
Varible neg : std_logic_vector(3 downto 0); //Variable is assigned after process
begin
if (sign_mag <= 1000) then //conditional operator
twos_comp<=sign_mag; //Output is assigned
else
neg :=('1' & not sign_mag(2 downto 0))+1; //Variable are assigned using := operator where as signal use<= operator
twos_comp<=neg;
end if;