Branch Predictors Designers of a new computer decided to implement a hybrid bran
ID: 3532397 • Letter: B
Question
Branch Predictors Designers of a new computer decided to implement a hybrid branch prediction scheme shown in the drawing below. The hybrid design comprises two branch prediction paths (local prediction, and correlating prediction). The local prediction uses a local history table to record the taken/not-taken history of a branch. For each branch, the local history table holds 2 bits of branch history, indexed by the instruction address. For each branch, local prediction uses the 2-bit local history to select from one of the four 1-bit prediction counters. Each 1-bit counter makes its prediction based on one of two possible values: 0 (not taken), and 1 (taken). The correlating prediction uses a 1-bit global register (g) to store the direction of the last branch executed (which may not be the same branch as the branch currently being predicted). For each branch (using instruction address as index), correlating prediction uses the 1 -bit global register (g) to select from one of the two 1-bit prediction counters. Each 1-bit counter makes its prediction based on one of two possible values: 0 (not taken), and 1 (taken). Note that 1-bit counter simply remembers the last branch outcome. Consider the following MIPS code segment (inside a program loop), Assume that the following list of nine values of R2 is to be processed by nine iterations of the loop. Fill in the predicted and actual branch directions of b2 for nine iterations of the loop. Assume initial values of g = 0, and 0 for all counters. Table below tracks the value of g, local history of b2, and predictor status.Explanation / Answer
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