A RISC machine may do both a mapping of symbolic registers to actual registers a
ID: 3555953 • Letter: A
Question
A RISC machine may do both a mapping of symbolic registers to actual registers and a rearrangement of instructions for pipeline efficiency. An interesting question arises a to the order in which these operations should be done. Consider the following program fragment:
LD SR1, A
LD SR2, B
ADD SR3, SR1, SR2
LD SR4, C
LD SR5, D
ADD SR6, SR4, SR5
First do the register mapping and then any possible instruction reordering. How many machine registers are used? Has there been any pipeline improvement?
Starting with the original program, now do the instruction reordering and then any possible mapping. How many machine registers are used? Has there been any pipeline improvement?
Explanation / Answer
S:=0; for K:=1 to 100 do S:=S-K; A straightforward translation of this into a generic assemblylanguage would look something like this: LD R1,0 ;keep value of S in R1 LD R2,1 ;keep value of K in R2 LP SUB R1,R1,R2 ;S:=S-K BEQ R2,100,EXIT ;done if K=100 ADD R2,R2,1 ;else increment K JMP LP ;back to the start of loop A compiler for a RISC machine will introduce delay slots in this code so that the processor can employ delayed branch mechanism. The JMP instruction is easy to dceal with, because this instruction is always followed by the SUB instruction; therefore we can simply place a copy of the SUB instruction in the delay slot after the JMP. The BEQ presents a difficulty. We can't leave the code as is, because the ADD instruction would then be exectued one too many time. Therefore a NOP instructions is need