Hello, I have written a code in VHDL named stopwatch. It runs like a stopwatch o

Question

Hello, I have written a code in VHDL named stopwatch. It runs like a stopwatch on a DE2 board I have purchased recently and it uses Cyclone II. It runs idependent of the each segement of time, meaning the cc runs independently of the seconds which run independently of the minutes. If you can help me to where each time runs off the other that would be much appreciated. For example once the seconds reach sixty then the minutes change to 1 and seconds restart its cycle. Below is the code I have.

library ieee;

use ieee.std_logic_1164.all;

entity stopwatch is
   port
   (
       clk : in std_logic;
       digit1 : out std_logic_vector(1 to 7);
       digit2 : out std_logic_vector(1 to 7);
       digit3 : out std_logic_vector(1 to 7);
       digit4 : out std_logic_vector(1 to 7);
       digit5 : out std_logic_vector(1 to 7);
       digit6 : out std_logic_vector(1 to 7);
       key : in std_logic_vector(0 to 1)
   );
end stopwatch;
  
architecture main_func of stopwatch is
   signal digit1_cnt : integer range 0 to 9;
   signal digit2_cnt : integer range 0 to 9;
   signal digit3_cnt : integer range 0 to 9;
   signal digit4_cnt : integer range 0 to 9;
   signal digit5_cnt : integer range 0 to 9;
   signal digit6_cnt : integer range 0 to 9;
   signal en : bit;
   signal push_button : bit;
  
begin
   process(clk)
   begin
       if clk = '1' and clk'event then  
           if key(0)='0' then
               en <= '1';
           else
               en <= '0';
           end if;
       end if;
   end process;
   process
   begin
       wait until en = '1' and en'event;
       push_button <= not push_button;
   end process;
  
   process
       variable clk_cnt_ms : integer;
       variable clk_cnt_ss : integer;
       variable flag : integer;
      
           function int2hex_disp(num : integer range 0 to 9)return std_logic_vector is
           variable temp : std_logic_vector(1 to 7);
  
   begin
       case num is
       when 0 => temp := "0000001";
       when 1 => temp := "1001111";
       when 2 => temp := "0010010";
       when 3 => temp := "0000110";
       when 4 => temp := "1001100";
       when 5 => temp := "0100100";
       when 6 => temp := "0100000";
       when 7 => temp := "0001111";
       when 8 => temp := "0000000";
               when others => temp := "0000100";
           end case;
           return temp;
       end int2hex_disp;
   begin
wait until clk = '1' and clk'event;
       -- Begin the miliseconds, normally put 50_000_000 / 100 which equals 500_000,
       -- Starts the count independent of the others
       if push_button = '1' then
           if clk_cnt_ms = 500_000 then
               clk_cnt_ms := 0;
               if digit1_cnt = 9 and digit2_cnt = 9 then
                   digit2_cnt <= 0;
                   digit1_cnt <= 0;
               else
                   if digit1_cnt = 9 then
                       digit2_cnt <= digit2_cnt + 1;
                       digit1_cnt <= 0;
                   else  
                           digit1_cnt <= digit1_cnt + 1;
               end if;
           end if;
           else
               clk_cnt_ms := clk_cnt_ms + 1;
       end if;
          
       -- Begins the seconds on the stopwatch
       -- Implement 50_000_000 beginning of second
       if clk_cnt_ss = 50_000_000 then
           clk_cnt_ss := 0;
           flag := 0;
           if digit3_cnt = 9 and digit4_cnt = 5 then
               digit4_cnt <= 0;
               digit3_cnt <= 0;
               flag := 1;
           else
               if digit3_cnt = 9 then
                   digit4_cnt <= digit4_cnt + 1;
                   digit3_cnt <= 0;
                   flag := 0;
               else  
                       digit3_cnt <= digit3_cnt + 1;
                       flag := 0;
               end if;
           end if;
       else
           clk_cnt_ss := clk_cnt_ss + 1;
           flag := 0;
       end if;
          
      
       if flag = 1 then
           flag := 0;
           if digit5_cnt = 9 and digit6_cnt = 5 then
               digit6_cnt <= 0;
               digit5_cnt <= 0;
           else
               if digit5_cnt = 9 then
                   digit6_cnt <= digit6_cnt + 1;
                   digit5_cnt <= 0;
               else  
                   digit5_cnt <= digit5_cnt + 1;
               end if;
           end if;
       end if;
       end if;
       -- Display and keys
       if key(1)='0' then
           digit1_cnt <= 0;
           digit2_cnt <= 0;
           digit3_cnt <= 0;
           digit4_cnt <= 0;
           digit5_cnt <= 0;
           digit6_cnt <= 0;
       end if;
       digit1 <= int2hex_disp(digit1_cnt);
       digit2 <= int2hex_disp(digit2_cnt);
       digit3 <= int2hex_disp(digit3_cnt);
       digit4 <= int2hex_disp(digit4_cnt);
       digit5 <= int2hex_disp(digit5_cnt);
       digit6 <= int2hex_disp(digit6_cnt);

   end process;
      

end main_func;

Explanation / Answer

Library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_arith.all; entity SWFINAL is port ( CLK: in STD_LOGIC; -- clock (36MHz) MR: in STD_LOGIC; -- master reset pin L,S: in STD_LOGIC; -- L-"light", S-"start/stop" of my wristwatch ENIN: in STD_LOGIC; -- enable RSTIN: in STD_LOGIC; -- reset RUNIN: in STD_LOGIC; -- start/stop ('1' means run) Q3: out STD_LOGIC_VECTOR (3 downto 0); -- 10 Sec Q2: out STD_LOGIC_VECTOR (3 downto 0); -- 1 Sec Q1: out STD_LOGIC_VECTOR (3 downto 0); -- 1/10 Sec Q0: out STD_LOGIC_VECTOR (3 downto 0) -- 1/100 Sec ); end SWFINAL; architecture SWFINAL_STR of SWFINAL is component SWFSM -- U1 port ( CLK: in STD_LOGIC; MR: in STD_LOGIC; L,S: in STD_LOGIC;-- L-"light", S-"start/stop" of my wristwatch EN, RUN, RST: out STD_LOGIC-- outputs to monitor "latch enable", "run stop", and "reset" conditions ); end component; component TIMER -- U2 port (C: in STD_LOGIC; -- clock (100Hz) EN: in STD_LOGIC; -- enable RST: in STD_LOGIC; -- reset RUN: in STD_LOGIC; -- start/stop ('1' means run) Q3: out STD_LOGIC_VECTOR (3 downto 0); -- 10 Sec Q2: out STD_LOGIC_VECTOR (3 downto 0); -- 1 Sec Q1: out STD_LOGIC_VECTOR (3 downto 0); -- 1/10 Sec Q0: out STD_LOGIC_VECTOR (3 downto 0)); -- 1/100 Sec end component; component CLKDIV2 -- U3 port (CLK: in STD_LOGIC; MR: in STD_LOGIC; SMCLK : out STD_LOGIC; SWCLK : out STD_LOGIC ); end component; signal DATA3, DATA2, DATA1, DATA0: STD_LOGIC_VECTOR(3 downto 0); signal SWCLKi, SMCLKi: STD_LOGIC; -- stopwatch and state machine clocks signal EN, RUN, RST: STD_LOGIC; -- stopwatch and state machine clocks signal ENi, RUNi, RSTi: STD_LOGIC; -- stopwatch and state machine clocks begin ENi

Related Questions

Navigate

• Browse (All)
• Browse H
• Subjects

---