2. Write VHDL program for the RTL schematic diagram shown below. 3 Write comment

Question

2. Write VHDL program for the RTL schematic diagram shown below.

3 Write comments on each line of the VHDL code that explains what it is and what its doing?

4. Explain the results that you will get when simulating this VHDL program and when you get the waveform diagram.

For best work I will give extra 1500 points.

3.

Develop a Quartus II project that implements a full-adder using two half-adders. The project must include a hierarchical structui?e consisting of a high-level entity/architecture pail? and a lower-level entity/architecture pair. Included in the high-level architecture is a component defmition for a half-adder and two instantiations of the half-addei?. The lower-level ai?chitectui?e defines the half-adder circuitry. 3 Write comments on each line of the VHDL code that explains what it is and what its doing? 4. Explain the results that you will get when simulating this VHDL program and when you get the waveform diagram. For best work I will give extra 1500 points. 3. 2. Write VHDL program for the RTL schematic diagram shown below.

Explanation / Answer

brary ieee; use ieee.std_logic_1164.all; --ENTITY DECLARATION: no inputs, no outputs entity andGate_tb is end andGate_tb; -- Describe how to test the AND Gate architecture tb of andGate_tb is --pass andGate entity to the testbench as component component andGate is port( A, B : in std_logic; F : out std_logic); end component; signal inA, inB, outF : std_logic; begin --map the testbench signals to the ports of the andGate mapping: andGate port map(inA, inB, outF); process --variable to track errors variable errCnt : integer := 0; begin --TEST 1 inA

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