Digital Logic Design, verilog 8-bit counter I don\'t quite understand this probl

Question

Digital Logic Design, verilog 8-bit counter

I don't quite understand this problem. Any help will be appreciated.

The structure of an 8-bit counter with general controls can be conceived as shown below. (a) Write down behavior -level Verilog descriptions for module 1, 2 and 3 respectively (with proper module names if possible). (b) Writel down behavior -level Verilog descriptions for the 8 -bit counter by instantiating the 3 modules from (a). (c) Though the 3 modules are specified by 1-0 relationships of each own without any information regarding interior structure, could you point out, based on the best knowledge of yours, the kind of the circuit that is most likely to be for each of the three? (d) What is the time limit within which that module 1 must complete the task of

Explanation / Answer

module behav_counter( d, clk, clear, load, up_down, qd); // Port Declaration input [7:0] d; input clk; input clear; input load; input up_down; output [7:0] qd; reg [7:0] cnt; assign qd = cnt; always @ (posedge clk) begin if (!clear) cnt = 8'h00; else if (load) cnt = d; else if (up_down) cnt = cnt + 1; else cnt = cnt - 1; end endmodule

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