I need some to help me to solve this question those question are related to VHDL
ID: 3566322 • Letter: I
Question
I need some to help me to solve this question those question are related to VHDL - digital logic design course .. Please need correct answer and some explaination, i would not grade if you post email or coments . thank you for help
1) ____ Which of the following lines best describes a big endian register of 64 bits?
a) Bigendian[64] register;
b) register : bigendian std_logic_vector;
c) register : inout std_logic_vector(63 downto 0);
d) register : inout std_logic_vector(0 to 63);
2) ____ If we create our own library named personal, how do we include all functions located in that library?
a) library ieee; use ieee.personal.all;
b) library work; use work.personal.all;
c) library personal; use personal.all;
d) library custom; use custom.personal.all;
3) ____ Given the following code:
first := X;
second := Y;
while (integer(second) /= 1) loop
if (second(0) = '1') then
res := res + first;
end if;
first := first sll 1;
second := second srl 1;
end loop;
return res;
What will be the output if X = 8 and Y = 5?
a) 8
b) 40
c) 32
d) 4
4) ____ On a
Explanation / Answer
ANS1: In big endian lowest position contains the most significant bit. Thus, the correct answer is
D) register :inout std_logic_vector(0 to 63);
As, the first to come in (0 to 63) here, i.e. 0, implies the position of the MSB
ANS2: Any library we create in VHDL is by default stored in the work directory. So the correct answer is:
b) library work; use work.personal.all;
However, the Xilinx tool provides with an option to create a custom library that is parallel to the work directory, thereby enabling the user not to always go to the work directory for new includes.
ANS3: a) 8
5 = 101
8 = 1000
as 101 is not equal to 1 we enter loop
second(0) = 1 thus res = 0 + 8 = 8
first = 10000
second = 10
so it enters loop but res remains same
In next loop, second becomes 1. Thus loop exits.
So, ans is 8
ANS4: d) when others
This will be default as it considers rest of the cases. Apart from that, its just syntax.
ANS5: You can do either, but ideally it should be a Signal. This is because VHDL is a synthesis language, so it should be preffered to use constructs that are synthesizeable. Signal is so but variable isn't always so.
ANS6: b) type mem is array(0 to 65535) of std_logic_vector(31 downto 0);
Two points to mention. The RAM is big endian, so (0 to 65535). The rest of it is because each bit points to a 32 bit address.
ANS7: Variables are never used in architecture. Apart from that := is the syntax for assigning integers. Thus,
a) In a process, num := value;
ANS8: b) param